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-- $(lic)
-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
use work.cache_config.all;
use work.gencmem_lib.all;
use work.int.all;
use work.memdef.all;

-- PREFIX: gdcl_xxx
package gendc_lib is

type gdcl_ctrl is record
  writeback : std_logic;
  allocateonstore : std_logic;
end record;

-- dcache tag layout
-- addr: |         tag         | (tag)addr | line | 00 |
--                                   |
--     +-----------------------------+
--     | +-------+---------------------+---------+
--     +>| DIRTY |       CLTAG         | CLVALID |
--       +-------+---------------------+---------+

-- addr to cmem-tag fields/access layout
constant GDCL_TTAG_D : integer  :=  2 + GCML_DC_TLINE_BSZ + GCML_DC_TADDR_BSZ;
constant GDCL_TTAG_U : integer  := (2 + GCML_DC_TLINE_BSZ + GCML_DC_TADDR_BSZ + GCML_DC_TTAG_BSZ) -1;
constant GDCL_TADDR_D : integer :=  2 + GCML_DC_TLINE_BSZ;
constant GDCL_TADDR_U : integer := (2 + GCML_DC_TLINE_BSZ + GCML_DC_TADDR_BSZ) -1;
constant GDCL_TLINE_D : integer :=  2;
constant GDCL_TLINE_U : integer := (2 + GCML_DC_TLINE_BSZ ) -1;

-- addr to cmem-data fields/access layout
constant GDCL_DADDR_D : integer :=  2 + GCML_DC_DLINE_BSZ;
constant GDCL_DADDR_U : integer := (2 + GCML_DC_DLINE_BSZ + GCML_DC_DADDR_BSZ) -1;
constant GDCL_DLINE_D : integer :=  2;
constant GDCL_DLINE_U : integer := (2 + GCML_DC_DLINE_BSZ ) -1;

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

function gdcl_is_taghit (
  addr : std_logic_vector(31 downto 0);
  cline : gcml_dc_tline
) return boolean;

function gdcl_is_linevalid (
  addr : std_logic_vector(31 downto 0);
  cline : gcml_dc_tline
) return boolean;

function gdcl_is_linedirty (
  addr : std_logic_vector(31 downto 0);
  cline : gcml_dc_tline
) return boolean;

function gdcl_is_free (
  cline : gcml_dc_tline
) return boolean;

function gdcl_is_dirty (
  cline : gcml_dc_tline
) return boolean;

function gdcl_getpos (
  addr : std_logic_vector(GCML_DC_TLINE_BSZ-1 downto 0)
) return integer;

function gdcl_readdata (
  addrlo : std_logic_vector(1 downto 0);
  data : std_logic_vector(31 downto 0);
  bo   : lmd_byteorder;
  sign : std_logic;
  size : lmd_memsize
) return std_logic_vector;

function gdcl_writedata (
  addrlo : std_logic_vector(1 downto 0);
  base : std_logic_vector(31 downto 0);
  data : std_logic_vector(31 downto 0);
  bo   : lmd_byteorder;
  size : lmd_memsize
) return std_logic_vector;

constant GDCL_ZERO_C  : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0) := (others => '0');
constant GDCL_LAST_C  : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0) := (others => '1');
constant GDCL_NLAST_C : std_logic_vector(CFG_DC_TLINE_SZ-2 downto 0) := (others => '1');

end gendc_lib;

package body gendc_lib is

function gdcl_writedata (
  addrlo : std_logic_vector(1 downto 0);
  base : std_logic_vector(31 downto 0);
  data : std_logic_vector(31 downto 0);
  bo   : lmd_byteorder;
  size : lmd_memsize
) return std_logic_vector is
  variable tmp  : std_logic_vector(31 downto 0);
begin
  tmp := base;
  if bo = lmd_little then
    -- lmd_little: byte[3 2 1 0], hw[1 0]
    case size is
      when lmd_byte => 
        case addrlo(1 downto 0) is
          when "00" => tmp( 7 downto  0) := data( 7 downto  0);
          when "01" => tmp(15 downto  8) := data( 7 downto  0);
          when "10" => tmp(23 downto 16) := data( 7 downto  0);
          when "11" => tmp(31 downto 24) := data( 7 downto  0);
          when others => null;
        end case;
      when lmd_half => 
        case addrlo(1 downto 1) is
          when "0"  => tmp(15 downto  0) := data(15 downto  0);
          when "1"  => tmp(31 downto 16) := data(15 downto  0);
          when others => null;
        end case;
      when others => tmp := data;
    end case;
  else
    -- lmd_big:    byte[0 1 2 3], hw[0 1]
    case size is
      when lmd_byte => 
        case addrlo(1 downto 0) is
          when "00" => tmp(31 downto 24) := data( 7 downto  0);
          when "01" => tmp(23 downto 16) := data( 7 downto  0);
          when "10" => tmp(15 downto  8) := data( 7 downto  0);
          when "11" => tmp( 7 downto  0) := data( 7 downto  0);
          when others => null;
        end case;
      when lmd_half => 
        case addrlo(1 downto 1) is
          when "0"  => tmp(31 downto 16) := data(15 downto  0);
          when "1"  => tmp(15 downto  0) := data(15 downto  0);
          when others => null;
        end case;
      when others => tmp := data;
    end case;
  end if;
  return tmp;
end;

function gdcl_readdata (
  addrlo : std_logic_vector(1 downto 0);
  data : std_logic_vector(31 downto 0);
  bo   : lmd_byteorder;
  sign : std_logic;
  size : lmd_memsize
) return std_logic_vector is
  variable tmp  : std_logic_vector(31 downto 0);
begin
  tmp := (others => '0');
  if bo = lmd_little then
    -- lmd_little: byte[3 2 1 0], hw[1 0]
    case size is
      when lmd_byte => 
        case addrlo(1 downto 0) is
          when "00" => tmp( 7 downto 0) := data( 7 downto  0);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data( 7));
                       end if;
          when "01" => tmp( 7 downto 0) := data(15 downto  8);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(15));
                       end if;
          when "10" => tmp( 7 downto 0) := data(23 downto 16);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(23));
                       end if;
          when "11" => tmp( 7 downto 0) := data(31 downto 24);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(31));
                       end if;
          when others => null;
        end case;
      when lmd_half => 
        case addrlo(1 downto 1) is
          when "0"  => tmp(15 downto 0) := data(15 downto  0);
                       if sign='1' then
                         tmp(31 downto 16) := (others => data( 15));
                       end if;
          when "1"  => tmp(15 downto 0) := data(31 downto  16);
                       if sign='1' then
                         tmp(31 downto 16) := (others => data(31));
                       end if;
          when others => null;
        end case;
      when others => tmp := data;
    end case;
  else
    -- lmd_big:    byte[0 1 2 3], hw[0 1]
    case size is
      when lmd_byte => 
        case addrlo(1 downto 0) is
          when "00" => tmp( 7 downto 0) := data(31 downto  24);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(31));
                       end if;
          when "01" => tmp( 7 downto 0) := data(23 downto 16);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(23));
                       end if;
          when "10" => tmp( 7 downto 0) := data(15 downto  8);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(16));
                       end if;
          when "11" => tmp( 7 downto 0) := data( 7 downto  0);
                       if sign='1' then
                         tmp(31 downto 8) := (others => data(7));
                       end if;
          when others => null;
        end case;
      when lmd_half => 
        case addrlo(1 downto 1) is
          when "0"  => tmp(15 downto 0) := data(31 downto  16);
                       if sign='1' then
                         tmp(31 downto 16) := (others => data(31));
                       end if;
          when "1"  => tmp(15 downto 0) := data(15 downto  0);
                       if sign='1' then
                         tmp(31 downto 16) := (others => data( 15));
                       end if;
          when others => null;
        end case;
      when others => tmp := data;
    end case;
  end if;
  return tmp;
end;

function gdcl_getpos (
  addr : std_logic_vector(GCML_DC_TLINE_BSZ-1 downto 0)
) return integer is
  variable tmp : integer;
begin
  tmp := 0;
  if CFG_DC_DLINE_SZ > 1 then
    tmp := lin_convint(addr(GCML_DC_DLINE_BSZ-1 downto 0));
  end if;
  return tmp;
end;
  
function gdcl_is_taghit (
  addr : std_logic_vector(31 downto 0);
  cline : gcml_dc_tline
) return boolean is
  variable tmp : boolean;
  variable tag : std_logic_vector(GDCL_TTAG_U downto GDCL_TTAG_D);
begin
  tmp := false;
  tag := addr(GDCL_TTAG_U downto GDCL_TTAG_D);
  if (tag = cline.tag) then
    tmp := true;
  end if;
  return tmp;
end;

function gdcl_is_linevalid (
  addr : std_logic_vector(31 downto 0);
  cline : gcml_dc_tline
) return boolean is
  variable tmp : boolean;
  variable line : std_logic_vector(GDCL_TLINE_U downto GDCL_TLINE_D);
begin
  tmp := false;
  line := addr(GDCL_TLINE_U downto GDCL_TLINE_D);
  if (cline.valid(lin_convint(line)) = '1')
  then
    tmp := true;
  end if;
  return tmp;
end;

function gdcl_is_linedirty (
  addr : std_logic_vector(31 downto 0);
  cline : gcml_dc_tline
) return boolean is
  variable tmp : boolean;
  variable line : std_logic_vector(GDCL_TLINE_U downto GDCL_TLINE_D);
begin
  tmp := false;
  line := addr(GDCL_TLINE_U downto GDCL_TLINE_D);
  if (cline.dirty(lin_convint(line)) = '1')
  then
    tmp := true;
  end if;
  return tmp;
end;

function gdcl_is_free (
  cline : gcml_dc_tline
) return boolean is
  variable tmp : boolean;
begin
  tmp := true;
  for i in CFG_DC_TLINE_SZ-1 downto 0 loop
    if cline.valid(i) = '1' then
      tmp := false;
    end if;
  end loop;  -- i
  return tmp;
end;

function gdcl_is_dirty (
  cline : gcml_dc_tline
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  for i in CFG_DC_TLINE_SZ-1 downto 0 loop
    if cline.dirty(i) = '1' then
      tmp := true;
    end if;
  end loop;  -- i
  return tmp;
end;
  
end gendc_lib;

File /tmp/build_html/soft/doc/test/.config.vhd used by /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/genic_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/genwb_lib.vhd used by /tmp/build_html/vhdl/mem/cache/cache_comp.vhd used by /tmp/build_html/vhdl/mem/cache/cache_comp.vhd used by /tmp/build_html/vhdl/mem/cache/genic.vhd used by /tmp/build_html/vhdl/mem/cache/genic.vhd used by /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd used by /tmp/build_html/vhdl/arith/cnt/arith_cnt8.vhd used by /tmp/build_html/vhdl/arm/libs/armshiefter.vhd used by /tmp/build_html/vhdl/arm/armiu_festg.vhd used by /tmp/build_html/vhdl/arm/cp/armcp_sctrl.vhd used by /tmp/build_html/vhdl/core/ctrl/rstgen.vhd used by /tmp/build_html/vhdl/arm/tbench_armcache.vhd used by /tmp/build_html/vhdl/m68k/libs/m68kdecode.vhd used by /tmp/build_html/vhdl/mem/cache/kecs_wb.vhd used by /tmp/build_html/vhdl/mem/cache/kecs_wbfifo.vhd used by /tmp/build_html/vhdl/sparc/leon_pci.vhd used by /tmp/build_html/vhdl/tbench/dep_tbgen.vhd

Enum rdatatype defined in /tmp/build_html/vhdl/sparc/mmu_icache.vhd type rdatatype is (itag, idata, memory);

File /tmp/build_html/vhdl/sparc/cache.vhd

Constant words defined in /tmp/build_html/vhdl/tech/tech_axcel.vhd constant words : integer := 2**abits;

Enum cache_replace_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd type cache_replace_type is (lru, lrr, rnd);

Enum astates defined in /tmp/build_html/vhdl/sparc/mmu_acache.vhd type astates is (idle, dcache, icache, mmu);

Enum cpins_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd type cpins_type is (none, cpop, load, store);

Enum dsnoop_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd type dsnoop_type is (none, slow, fast);

Enum txfsmtype defined in /tmp/build_html/vhdl/sparc/dcom_uart.vhd type txfsmtype is (idle, data, stopbit);

Enum areatype defined in /tmp/build_html/vhdl/peripherals/mem/mctrl.vhd type areatype is (rom, io, ram);

Enum fpu_state defined in /tmp/build_html/vhdl/sparc/fpu_lth.vhd type fpu_state is (start, get_operand, pre_norm, add_sub, post_norm, rnd_norm, hold_val);

Type cache_config_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd type cache_config_type is record isets : integer range 1 to 4; -- # of sets in icache isetsize : integer; -- I-cache size per set in Kbytes ilinesize : integer; -- # words per I-cache line ireplace : cache_replace_type; -- icache replacement algorithm ilock : integer; -- icache locking dsets : integer range 1 to 4; -- # of sets in dcache dsetsize : integer; -- D-cache size per set in Kbytes dlinesize : integer; -- # words per D-cache line dreplace : cache_replace_type; -- icache replacement algorithm dlock : integer; -- dcache locking dsnoop : dsnoop_type; -- data-cache snooping drfast : boolean; -- data-cache fast read-data generation dwfast : boolean; -- data-cache fast write-data generation dlram : boolean; -- local data ram enable dlramsize : integer; -- local data ram size in kbytes dlramaddr : integer; -- local data ram start address (8 msb) end record;

Constant cache_config defined in /tmp/build_html/vhdl/sparc/leon_device.vhd constant cache_config : cache_config_type := ( isets =>

File /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/genic_lib.vhd used by /tmp/build_html/vhdl/mem/cache/cache_comp.vhd used by /tmp/build_html/vhdl/mem/cache/gencmem.vhd used by /tmp/build_html/vhdl/mem/cache/genic.vhd used by /tmp/build_html/vhdl/mem/cache/gendc.vhd

File /tmp/build_html/vhdl/libs/int.vhd used by /tmp/build_html/vhdl/core/ctrl/irqctrl.vhd used by /tmp/build_html/vhdl/bus/ahbmst_mp.vhd used by /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/genic_lib.vhd used by /tmp/build_html/vhdl/mem/cache/genic.vhd used by /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd used by /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd used by /tmp/build_html/vhdl/mem/cache/setrepl.vhd used by /tmp/build_html/vhdl/mem/cache/gendc.vhd used by /tmp/build_html/vhdl/arm/arm_comp.vhd used by /tmp/build_html/vhdl/arm/armiu_festg.vhd used by /tmp/build_html/vhdl/arm/libs/armcmd.vhd used by /tmp/build_html/vhdl/arm/armcmd_cr.vhd used by /tmp/build_html/vhdl/arm/armcmd_cs.vhd used by /tmp/build_html/vhdl/arm/armiu_drstg.vhd used by /tmp/build_html/vhdl/arm/armiu_rsstg.vhd used by /tmp/build_html/vhdl/arm/cp/armcp_comp.vhd used by /tmp/build_html/soft/doc/test/.config.vhd

File /tmp/build_html/vhdl/libs/memdef.vhd used by /tmp/build_html/vhdl/config.vhd used by /tmp/build_html/vhdl/bus/bus_comp.vhd used by /tmp/build_html/vhdl/bus/ahbmst_mp.vhd used by /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd used by /tmp/build_html/vhdl/mem/cache/libs/genwb_lib.vhd used by /tmp/build_html/vhdl/mem/cache/genic.vhd used by /tmp/build_html/vhdl/mem/cache/genwb.vhd used by /tmp/build_html/vhdl/mem/cache/gendc.vhd used by /tmp/build_html/vhdl/arm/libs/armshiefter.vhd used by /tmp/build_html/vhdl/arm/armiu_festg.vhd used by /tmp/build_html/vhdl/arm/libs/armcmd.vhd used by /tmp/build_html/vhdl/arm/armcmd_sm.vhd used by /tmp/build_html/vhdl/arm/armcmd_cr.vhd used by /tmp/build_html/vhdl/arm/armcmd_cs.vhd used by /tmp/build_html/vhdl/arm/armiu_rsstg.vhd used by /tmp/build_html/vhdl/arm/cp/armcp_sctrl.vhd used by /tmp/build_html/soft/doc/test/.config.vhd

File /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd used by /tmp/build_html/vhdl/mem/cache/cache_comp.vhd used by /tmp/build_html/vhdl/mem/cache/gencmem.vhd used by /tmp/build_html/vhdl/mem/cache/gendc.vhd used by /tmp/build_html/vhdl/arm/armcache.vhd used by /tmp/build_html/vhdl/arm/libs/armpctrl.vhd used by /tmp/build_html/vhdl/arm/libs/armcmd.vhd used by /tmp/build_html/vhdl/arm/libs/armldst.vhd used by /tmp/build_html/vhdl/arm/armcmd_comp.vhd used by /tmp/build_html/vhdl/arm/armcmd_ld.vhd used by /tmp/build_html/vhdl/arm/armcmd_st.vhd used by /tmp/build_html/soft/doc/test/.config.vhd

Type gdcl_ctrl defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd type gdcl_ctrl is record writeback : std_logic; allocateonstore : std_logic; end record;

Constant CFG_DC_DLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd constant CFG_DC_DLINE_SZ : integer range 1 to 8 := 1;

Type gcml_dc_dline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd type gcml_dc_dline is record data : std_logic_vector_a(CFG_DC_DLINE_SZ-1 downto 0); end record;

Constant lin_log2 defined in /tmp/build_html/vhdl/libs/int.vhd constant lin_log2 : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4, 5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Constant CFG_DC_TLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd constant CFG_DC_TLINE_SZ : integer range 2 to 8 := 4;

Constant GCML_DC_TLINE_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd constant GCML_DC_TLINE_BSZ : integer := lin_log2(CFG_DC_TLINE_SZ);

Constant CFG_DC_SET_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd constant CFG_DC_SET_SZ : integer range 1 to 64 := 1;

Constant GCML_DC_TADDR_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd constant GCML_DC_TADDR_BSZ : integer := ((8 +lin_log2(CFG_DC_SET_SZ))-lin_log2(CFG_DC_TLINE_SZ));

Constant GDCL_TTAG_D defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_TTAG_D : integer := 2 + GCML_DC_TLINE_BSZ + GCML_DC_TADDR_BSZ;

Constant CFG_DC_ADDR_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd constant CFG_DC_ADDR_SZ : integer := 32;

Constant GCML_DC_TTAG_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd constant GCML_DC_TTAG_BSZ : integer := CFG_DC_ADDR_SZ - (2 + (8 +lin_log2(CFG_DC_SET_SZ)));

Constant GDCL_TTAG_U defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_TTAG_U : integer := (2 + GCML_DC_TLINE_BSZ + GCML_DC_TADDR_BSZ + GCML_DC_TTAG_BSZ) -1;

Constant GDCL_TADDR_D defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_TADDR_D : integer := 2 + GCML_DC_TLINE_BSZ;

Constant GDCL_TADDR_U defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_TADDR_U : integer := (2 + GCML_DC_TLINE_BSZ + GCML_DC_TADDR_BSZ) -1;

Constant GDCL_TLINE_D defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_TLINE_D : integer := 2;

Constant GDCL_TLINE_U defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_TLINE_U : integer := (2 + GCML_DC_TLINE_BSZ ) -1;

Constant GCML_DC_DLINE_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd constant GCML_DC_DLINE_BSZ : integer := lin_log2(CFG_DC_DLINE_SZ);

Constant GDCL_DADDR_D defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_DADDR_D : integer := 2 + GCML_DC_DLINE_BSZ;

Constant GCML_DC_DADDR_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd constant GCML_DC_DADDR_BSZ : integer := ((8 +lin_log2(CFG_DC_SET_SZ))-lin_log2(CFG_DC_DLINE_SZ));

Constant GDCL_DADDR_U defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_DADDR_U : integer := (2 + GCML_DC_DLINE_BSZ + GCML_DC_DADDR_BSZ) -1;

Constant GDCL_DLINE_D defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_DLINE_D : integer := 2;

Constant GDCL_DLINE_U defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_DLINE_U : integer := (2 + GCML_DC_DLINE_BSZ ) -1;

Enum lmd_memsize defined in /tmp/build_html/vhdl/libs/memdef.vhd type lmd_memsize is ( lmd_word, lmd_byte, lmd_half, lmd_dbl );

Type gdcl_param defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd type gdcl_param is record size : lmd_memsize; read : std_logic; lock : std_logic; writedata : std_logic; addrin : std_logic; signed : std_logic; end record;

Type gcml_dc_tline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd type gcml_dc_tline is record tag : std_logic_vector(GCML_DC_TTAG_BSZ-1 downto 0); valid : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0); dirty : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0); lock : std_logic; end record;

Function gdcl_is_taghit defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_is_taghit ( addr : std_logic_vector(31 downto 0); cline : gcml_dc_tline ) return boolean is variable tmp : boolean; variable tag : std_logic_vector(GDCL_TTAG_U downto GDCL_TTAG_D); begin tmp := false; tag := addr(GDCL_TTAG_U downto GDCL_TTAG_D); if (tag = cline.tag) then tmp := true; end if; return tmp; end;

Function gdcl_is_linevalid defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_is_linevalid ( addr : std_logic_vector(31 downto 0); cline : gcml_dc_tline ) return boolean is variable tmp : boolean; variable line : std_logic_vector(GDCL_TLINE_U downto GDCL_TLINE_D); begin tmp := false; line := addr(GDCL_TLINE_U downto GDCL_TLINE_D); if (cline.valid(lin_convint(line)) = '1') then tmp := true; end if; return tmp; end;

Function gdcl_is_linedirty defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_is_linedirty ( addr : std_logic_vector(31 downto 0); cline : gcml_dc_tline ) return boolean is variable tmp : boolean; variable line : std_logic_vector(GDCL_TLINE_U downto GDCL_TLINE_D); begin tmp := false; line := addr(GDCL_TLINE_U downto GDCL_TLINE_D); if (cline.dirty(lin_convint(line)) = '1') then tmp := true; end if; return tmp; end;

Function gdcl_is_free defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_is_free ( cline : gcml_dc_tline ) return boolean is variable tmp : boolean; begin tmp := true; for i in CFG_DC_TLINE_SZ-1 downto 0 loop if cline.valid(i) = '1' then tmp := false; end if; end loop; -- i return tmp; end;

Function gdcl_is_dirty defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_is_dirty ( cline : gcml_dc_tline ) return boolean is variable tmp : boolean; begin tmp := false; for i in CFG_DC_TLINE_SZ-1 downto 0 loop if cline.dirty(i) = '1' then tmp := true; end if; end loop; -- i return tmp; end;

Function lin_convint defined in /tmp/build_html/vhdl/libs/int.vhd function lin_convint ( op : in std_logic_vector ) return integer is variable tmp : integer; begin tmp := 0; -- pragma translate_off if not (is_x(op)) then -- pragma translate_on tmp := conv_integer(op); -- pragma translate_off end if; -- pragma translate_on return tmp; end;

Function gdcl_getpos defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_getpos ( addr : std_logic_vector(GCML_DC_TLINE_BSZ-1 downto 0) ) return integer is variable tmp : integer; begin tmp := 0; if CFG_DC_DLINE_SZ > 1 then tmp := lin_convint(addr(GCML_DC_DLINE_BSZ-1 downto 0)); end if; return tmp; end;

Enum lmd_byteorder defined in /tmp/build_html/vhdl/libs/memdef.vhd type lmd_byteorder is (lmd_big, lmd_little);

Function gdcl_readdata defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd function gdcl_readdata ( addrlo : std_logic_vector(1 downto 0); data : std_logic_vector(31 downto 0); bo : lmd_byteorder; sign : std_logic; size : lmd_memsize ) return std_logic_vector is variable tmp : std_logic_vector(31 downto 0); begin tmp := (others => '0'); if bo = lmd_little then -- lmd_little: byte[3 2 1 0], hw[1 0] case size is when lmd_byte => case addrlo(1 downto 0) is when "00" => tmp( 7 downto 0) := data( 7 downto 0); if sign='1' then tmp(31 downto 8) := (others => data( 7)); end if; when "01" => tmp( 7 downto 0) := data(15 downto 8); if sign='1' then tmp(31 downto 8) := (others => data(15)); end if; when "10" => tmp( 7 downto 0) := data(23 downto 16); if sign='1' then tmp(31 downto 8) := (others => data(23)); end if; when "11" => tmp( 7 downto 0) := data(31 downto 24); if sign='1' then tmp(31 downto 8) := (others => data(31)); end if; when others => null; end case; when lmd_half => case addrlo(1 downto 1) is when "0" => tmp(15 downto 0) := data(15 downto 0); if sign='1' then tmp(31 downto 16) := (others => data( 15)); end if; when "1" => tmp(15 downto 0) := data(31 downto 16); if sign='1' then tmp(31 downto 16) := (others => data(31)); end if; when others => null; end case; when others => tmp := data; end case; else -- lmd_big: byte[0 1 2 3], hw[0 1] case size is when lmd_byte => case addrlo(1 downto 0) is when "00" => tmp( 7 downto 0) := data(31 downto 24); if sign='1' then tmp(31 downto 8) := (others => data(31)); end if; when "01" => tmp( 7 downto 0) := data(23 downto 16); if sign='1' then tmp(31 downto 8) := (others => data(23)); end if; when "10" => tmp( 7 downto 0) := data(15 downto 8); if sign='1' then tmp(31 downto 8) := (others => data(16)); end if; when "11" => tmp( 7 downto 0) := data( 7 downto 0); if sign='1' then tmp(31 downto 8) := (others => data(7)); end if; when others => null; end case; when lmd_half => case addrlo(1 downto 1) is when "0" => tmp(15 downto 0) := data(31 downto 16); if sign='1' then tmp(31 downto 16) := (others => data(31)); end if; when "1" => tmp(15 downto 0) := data(15 downto 0); if sign='1' then tmp(31 downto 16) := (others => data( 15)); end if; when others => null; end case; when others => tmp := data; end case; end if; return tmp; end;

Constant GDCL_ZERO_C defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_ZERO_C : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0) := (others =>

Constant GDCL_LAST_C defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_LAST_C : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0) := (others =>

Constant GDCL_NLAST_C defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd constant GDCL_NLAST_C : std_logic_vector(CFG_DC_TLINE_SZ-2 downto 0) := (others =>

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution