/tmp/build_html/vhdl/mem/cache/genwbfifo.vhd : l8arm - synthesizable ARM v4 vhdl model.

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-- $(lic)
-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
use work.int.all;
use work.genwb_lib.all;
use work.cache_comp.all;
use work.cache_config.all;
use work.tech_map.all;

entity genwbfifo is
  generic (
    WBBUF_SZ : integer := 2
  );
  port ( 
    rst : in  std_logic; 
    clk : in  std_logic;
    i : in  genwbfifo_type_in;
    o : out genwbfifo_type_out
  );
end genwbfifo;

architecture rtl of genwbfifo is

  type genwbfifo_tmp_type is record
     o : genwbfifo_type_out;
     readint, writeint : std_logic;
     
  end record;
  type genwbfifo_reg_type is record
     buf : gwbl_entry_a((WBBUF_SZ)-1 downto 0);
     cur, set : std_logic_vector((lin_log2(WBBUF_SZ))-1 downto 0);
     empty : std_logic;
  end record;
  type genwbfifo_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     wbaddr : std_logic_vector(31 downto 0);
     dbg : genwbfifo_tmp_type;
     -- pragma translate_on
  end record;
  signal r, c       : genwbfifo_reg_type;
  signal rdbg, cdbg : genwbfifo_dbg_type;
  
  
begin  
    
  p0: process (clk, rst, r, i )
    variable v    : genwbfifo_reg_type;
    variable t    : genwbfifo_tmp_type;
    variable vdbg : genwbfifo_dbg_type;
  begin 
    
    -- $(init(t:genwbfifo_tmp_type))
    v := r;


    --$(del)             o.entry_r  
    --       +-------+ <-cur   /\
    --       | xxxxx |  -------+ 
    --       +-------+
    --       | xxxxx |
    --       +-------+ <-set
    --       |       |
    --       .       .
    --       .       .
    --       +-------+
    --       |       |
    --       +-------+
    --$(/del)

    t.o.fifo_entry := r.buf(lin_convint(r.cur));
    t.o.fifo_empty_r := r.empty;
    
    t.readint := i.fifo_read;
    t.writeint := i.fifo_write;
    t.o.fifo_stored_v := i.fifo_write;
      
    if t.writeint = '1' then
      if r.cur = r.set then
        if (r.empty = '0') then
          if (i.fifo_read = '0') then
            t.writeint := '0';
            t.o.fifo_stored_v := '0';
          end if;
        end if;
      end if;
      if t.writeint = '1' then
        v.buf(lin_convint(r.set)) := i.fifo_entry;
        lin_incdec(r.set,v.set,'1','1');
        v.empty := '0';
      end if;
    end if;
    
    if t.readint = '1' then
      lin_incdec(r.cur,v.cur,'1','1');
      if v.cur = v.set then
        if t.o.fifo_stored_v = '0' then
          v.empty := '1';
        end if;
      end if;
    end if;
    
    
    -- reset
    if ( rst = '0' ) then
      v.empty := '1';
      v.cur := (others => '0');
      v.set := (others => '0');
    end if;
    
    c <= v;

    o <= t.o;
    
    -- pragma translate_off
    vdbg := rdbg;
    vdbg.dbg := t;
    cdbg <= vdbg;
    -- pragma translate_on  end process p0;
    
  end process p0;
    
  pregs : process (clk, c)
  begin
    if rising_edge(clk) then
      r <= c;
      -- pragma translate_off
      rdbg <= cdbg;
      -- pragma translate_on
    end if;
  end process;

  -- pragma translate_off
  check0 : process (clk)
  begin
    if falling_edge(clk) then
      if i.fifo_read = '1' then
        assert (r.empty = '0') report "Read on empty fifo" severity failure;
      end if;
    end if;
  end process;
  -- pragma translate_on  end process p0;

end rtl;

File /tmp/build_html/vhdl/mem/cache/libs/genwb_lib.vhd
used by /tmp/build_html/vhdl/mem/cache/cache_comp.vhd
used by /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd
used by /tmp/build_html/vhdl/mem/cache/genwb.vhd
used by /tmp/build_html/vhdl/mem/cache/gendc.vhd

Enum rdatatype defined in /tmp/build_html/vhdl/sparc/mmu_icache.vhd

type rdatatype is (itag, idata, memory);

File /tmp/build_html/vhdl/sparc/cache.vhd

Constant words defined in /tmp/build_html/vhdl/tech/tech_axcel.vhd

constant words : integer := 2**abits;

Enum cache_replace_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

type cache_replace_type is (lru, lrr, rnd);

Enum astates defined in /tmp/build_html/vhdl/sparc/mmu_acache.vhd

type astates is (idle, dcache, icache, mmu);

Enum cpins_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type cpins_type is (none, cpop, load, store);

Enum dsnoop_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

type dsnoop_type is (none, slow, fast);

Enum txfsmtype defined in /tmp/build_html/vhdl/sparc/dcom_uart.vhd

type txfsmtype is (idle, data, stopbit);

Enum areatype defined in /tmp/build_html/vhdl/peripherals/mem/mctrl.vhd

type areatype is (rom, io, ram);

Enum fpu_state defined in /tmp/build_html/vhdl/sparc/fpu_lth.vhd

type fpu_state is (start, get_operand, pre_norm, add_sub, post_norm,
                   rnd_norm, hold_val);

Type cache_config_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

type cache_config_type is record
  isets         : integer range 1 to 4;   -- # of sets in icache
  isetsize	: integer;	-- I-cache size per set in Kbytes
  ilinesize	: integer;	-- # words per I-cache line
  ireplace      : cache_replace_type;         -- icache replacement algorithm
  ilock     	: integer;	-- icache locking
  dsets         : integer range 1 to 4;   -- # of sets in dcache
  dsetsize	: integer;	-- D-cache size per set in Kbytes
  dlinesize	: integer;	-- # words per D-cache line
  dreplace      : cache_replace_type;         -- icache replacement algorithm
  dlock     	: integer;	-- dcache locking
  dsnoop    	: dsnoop_type;	-- data-cache snooping
  drfast    	: boolean;	-- data-cache fast read-data generation
  dwfast    	: boolean;	-- data-cache fast write-data generation
  dlram     	: boolean;	-- local data ram enable
  dlramsize 	: integer;	-- local data ram size in kbytes
  dlramaddr 	: integer;	-- local data ram start address (8 msb)
end record;

Constant cache_config defined in /tmp/build_html/vhdl/sparc/leon_device.vhd

constant cache_config : cache_config_type := (
    isets =>

File /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd

Enum lmd_memsize defined in /tmp/build_html/vhdl/libs/memdef.vhd

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

Enum ahbmst_state_type defined in /tmp/build_html/vhdl/sparc/pci_oc.vhd

type ahbmst_state_type is (idle, req, respond);

Type gwbl_entry defined in /tmp/build_html/vhdl/mem/cache/libs/genwb_lib.vhd

type gwbl_entry is record
  addr : std_logic_vector(31 downto 0);
  data : std_logic_vector(31 downto 0);
  burst : std_logic;
  size : lmd_memsize;
  read : std_logic;
  lock : std_logic;                     -- lock until next req
end record;

Type genwbfifo_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genwbfifo_type_in is record
  fifo_entry : gwbl_entry;
  fifo_read, fifo_write : std_logic;
end record;

Type genwbfifo_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genwbfifo_type_out is record
  fifo_entry : gwbl_entry;
  fifo_stored_v : std_logic;
  fifo_empty_r : std_logic;
end record;

Type genwbfifo_tmp_type defined in /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd

type genwbfifo_tmp_type is record
     o : genwbfifo_type_out;
     readint, writeint : std_logic;
     
  end record;

Constant lin_log2 defined in /tmp/build_html/vhdl/libs/int.vhd

constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Type genwbfifo_reg_type defined in /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd

type genwbfifo_reg_type is record
     buf : gwbl_entry_a((WBBUF_SZ)-1 downto 0);
     cur, set : std_logic_vector((lin_log2(WBBUF_SZ))-1 downto 0);
     empty : std_logic;
  end record;

Type genwbfifo_dbg_type defined in /tmp/build_html/vhdl/mem/cache/genwbfifo.vhd

type genwbfifo_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     wbaddr : std_logic_vector(31 downto 0);
     dbg : genwbfifo_tmp_type;
     -- pragma translate_on
  end record;

Function lin_convint defined in /tmp/build_html/vhdl/libs/int.vhd

function lin_convint (
  op   : in std_logic_vector
) return integer is
variable tmp : integer;
begin
  tmp := 0;
-- pragma translate_off
    if not (is_x(op)) then
-- pragma translate_on
      tmp := conv_integer(op);
-- pragma translate_off
    end if;
-- pragma translate_on
  return tmp;
end;

Function lin_decode defined in /tmp/build_html/vhdl/libs/int.vhd

function lin_decode(
  v : std_logic_vector
) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
  res := (others => '0');
-- pragma translate_off
  i := 0;
  if not is_x(v) then
-- pragma translate_on
    i := conv_integer(unsigned(v));
    res(i) := '1';
-- pragma translate_off
  else
    res := (others => 'X');
  end if;
-- pragma translate_on
  return(res);
end;

Constant lin_log2x defined in /tmp/build_html/vhdl/libs/int.vhd

constant lin_log2x : lin_log2arr := (1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Function lin_countzero defined in /tmp/build_html/vhdl/libs/int.vhd

function lin_countzero(
  data : in    std_logic_vector
) return std_logic_vector is
variable z02 : std_logic_vector((data'length/2)-1 downto 0);
variable z04 : std_logic_vector((data'length/4)-1 downto 0);
variable d04 : std_logic_vector(3 downto 0);
variable z08 : std_logic_vector((data'length/8)-1 downto 0);
variable d08 : std_logic_vector(7 downto 0);
variable z16 : std_logic_vector((data'length/16)-1 downto 0);
variable d16 : std_logic_vector(15 downto 0);
variable z32 : std_logic_vector((data'length/32)-1 downto 0);
variable d32 : std_logic_vector(31 downto 0);
variable z64 : std_logic_vector((data'length/64)-1 downto 0);
variable d64 : std_logic_vector(63 downto 0);
variable res : std_logic_vector(lin_log2x(data'length)-1 downto 0);
variable length : integer;
variable tmp : integer;
begin

  res := (others => '0');
  z32 := (others => '0');
  z02 := (others => '0');
  z04 := (others => '0');
  length := data'length;
  
  if (length / 2) >= 1 then
    tmp := 0;
L02:
    for i in (length/2)-1 downto 0 loop
      tmp := i;
      if    (data((i*2)+0) = '1') then
        z02(i) := '1';
        exit L02;
      elsif (data((i*2)+1) = '1') then
        z02(i) := '0';
        exit L02;
      else
        z02(i) := '0';
      end if;
    end loop;  -- i
    if (length = 2) then
      res(0) := z02(tmp);
    end if;
  end if;
  
  if (length / 4) >= 1 then
    tmp := 0;
L04:
    for i in (length/4)-1 downto 0 loop
      tmp := i;
      d04 := data((i*4)+3 downto i*4);
      z04(i) := '1';
      if    not (d04(3 downto 2) = "00") then
        z04(i) := '1';
        res(0) := z02(i*2);
        exit L04;
      elsif not (d04(1 downto 0) = "00") then
        z04(i) := '0';
        res(0) := z02((i*2)+1);
        exit L04;
      else
        z04(i) := '0';
      end if;
    end loop;  -- i
    if (length = 4) then
      res(1) := z04(tmp);
    end if;
  end if;
  
  if (length / 8) >= 1 then
    tmp := 0;
L08:
    for i in (length/8)-1 downto 0 loop
      tmp := i;
      d08 := data((i*8)+7 downto i*8);
      z08(i) := '1';
      if    not (d08(7 downto 4) = "0000") then
        z08(i) := '1';
        res(1) := z04(i*2);
        exit L08;
      elsif not (d08(3 downto 0) = "0000") then
        z08(i) := '0';
        res(1) := z04((i*2)+1);
        exit L08;
      else
        z08(i) := '0';
      end if;
    end loop;  -- i
    if (length = 8) then
      res(2) := z08(tmp);
    end if;
  end if;
  
  if (length / 16) >= 1 then
    tmp := 0;
L16:
    for i in (length/16)-1 downto 0 loop
      tmp := i;
      d16 := data((i*16)+15 downto i*16);
      z16(i) := '1';
      if    not (d16(15 downto 8) = "00000000") then
        z16(i) := '1';
        res(2) := z08(i*2);
        exit L16;
      elsif not (d16(7 downto 0) = "00000000") then
        z16(i) := '0';
        res(2) := z08((i*2)+1);
        exit L16;
      else
        z16(i) := '0';
      end if;
    end loop;  -- i
    if (length = 16) then
      res(3) := z16(tmp);
    end if;
  end if;

  if (length / 32) >= 1 then
    tmp := 0;
L32:
    for i in (length/32)-1 downto 0 loop
      tmp := i;
      d32 := data((i*32)+31 downto i*32);
      z32(i) := '1';
      if    not (d32(31 downto 16) = "0000000000000000") then
        z32(i) := '1';
        res(3) := z16(i*2);
        exit L32;
      elsif not (d32(15 downto 0) = "0000000000000000") then
        z32(i) := '0';
        res(3) := z16((i*2)+1);
        exit L32;
      else
        z32(i) := '0';
      end if;
    end loop;  -- i
    if (length = 32) then
      res(4) := z32(tmp);
    end if;
  end if;
  
  if (length / 64) >= 1 then
    tmp := 0;
L64:
    for i in (length/64)-1 downto 0 loop
      tmp := i;
      d64 := data((i*64)+63 downto i*64);
      z64(i) := '1';
      if    not (d64(63 downto 32) = "00000000000000000000000000000000") then
        z64(i) := '1';
        res(4) := z32(i*2);
        exit L64;
      elsif not (d64(31 downto 0) = "00000000000000000000000000000000") then
        z64(i) := '0';
        res(4) := z32((i*2)+1);
        exit L64;
      else
        z64(i) := '0';
      end if;
    end loop;  -- i
    if (length = 64) then
      res(5) := z64(tmp);
    end if;
  end if;

  return res;
end;

Procedure lin_adder defined in /tmp/build_html/vhdl/libs/int.vhd

procedure lin_adder(
  op1   : in std_logic_vector(31 downto 0);
  op2   : in std_logic_vector(31 downto 0);
  carry : in std_logic;
  sub   : in std_logic;
  sum   : out std_logic_vector(31 downto 0)
) is
begin
-- pragma translate_off
    if not (is_x(op1) or is_x(op2) or is_x(carry)) then
-- pragma translate_on
      if sub = '1' then
        sum := op1 - op2 - carry;
      else
        sum := op1 + op2 + carry;
      end if;
-- pragma translate_off
    else
      sum := (others => 'X');
    end if;
-- pragma translate_on

end;

Constant log2 defined in /tmp/build_html/vhdl/sparc/leon_config.vhd

constant log2  : log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Procedure lin_incdec defined in /tmp/build_html/vhdl/libs/int.vhd

procedure lin_incdec(
  source : in    std_logic_vector;
  dest   : inout std_logic_vector;
  do     : in    std_logic;
  inc    : in    std_logic
);
  
-- convert std_logic_vector to integer
function lin_convint(
  op   : in std_logic_vector
) return integer;

-- set bit integer(v)
function lin_decode(
  v : std_logic_vector
) return std_logic_vector;

-- pos of first '1' from left
function lin_countzero(
  data : in    std_logic_vector
) return std_logic_vector;

-- adder with carryin
procedure lin_adder(
  op1   : in std_logic_vector(31 downto 0);
  op2   : in std_logic_vector(31 downto 0);
  carry : in std_logic;
  sub   : in std_logic;
  sum   : out std_logic_vector(31 downto 0)
);

----------------------------------------------------------------------------
-- log2 tables
----------------------------------------------------------------------------

type lin_log2arr is array(1 to 64) of integer;
constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others => 6);
constant lin_log2x : lin_log2arr := (1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others => 6);

end int;

package body int is
  
procedure lin_incdec(
  source : in    std_logic_vector;
  dest   : inout std_logic_vector;
  do     : in    std_logic;
  inc    : in    std_logic
) is
variable tmp : std_logic_vector(source'range);
begin

  tmp := (others => '0');
-- pragma translate_off
    if not is_x(source) then
-- pragma translate_on
      if inc = '1' then
        tmp := source(source'range) + 1;
      else
        tmp := source(source'range) - 1;
      end if;
-- pragma translate_off
    else
      tmp := (others => 'X');
    end if;
-- pragma translate_on

    if (do) = '1' then
      dest := tmp;
    end if;

end;

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution