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[Donate]
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
use work.int.all;
use work.memdef.all;
use work.bus_comp.all;
use work.cache_comp.all;
use work.cache_config.all;
use work.genwb_lib.all;
entity genwb is
port (
rst : in std_logic;
clk : in std_logic;
i : in genwb_type_in;
o : out genwb_type_out;
mcwbo : in ahbmst_mp_out;
mcwbi : out ahbmst_mp_in
);
end genwb;
architecture rtl of genwb is
type kecswb_tmp_type is record
o : genwb_type_out;
wbfifoi : genwbfifo_type_in;
consume, req : std_logic;
end record;
type kecswb_reg_type is record
active : std_logic;
data : std_logic_vector(31 downto 0);
mcwbi : ahbmst_mp_in;
retry_mcwbi,buf_mcwbi : ahbmst_mp_in;
end record;
type kecswb_dbg_type is record
dummy : std_logic;
dbg : kecswb_tmp_type;
end record;
signal r, c : kecswb_reg_type;
signal rdbg, cdbg : kecswb_dbg_type;
signal wbfifoi : genwbfifo_type_in;
signal wbfifoo : genwbfifo_type_out;
begin
p0: process (clk, rst, r, i, mcwbo, wbfifoo )
variable v : kecswb_reg_type;
variable t : kecswb_tmp_type;
variable vdbg : kecswb_dbg_type;
begin
v := r;
t.wbfifoi.fifo_read := '0';
t.wbfifoi.fifo_entry := i.fifo_entry;
t.wbfifoi.fifo_write := i.fifo_write;
t.o.fifo_stored_v := wbfifoo.fifo_stored_v;
t.o.empty_v := wbfifoo.fifo_empty_r and (not r.mcwbi.req) and (not r.active); t.o.read_finish_v := '0';
t.o.read_mexc := mcwbo.mexc;
t.o.read_data := mcwbo.data;
t.req := (not wbfifoo.fifo_empty_r) or (i.fifo_write);
t.consume := '0';
if mcwbo.ready = '1' then
v.active := '0';
t.o.read_finish_v := r.retry_mcwbi.read;
end if;
if v.active = '0' then
if r.mcwbi.req = '0' and t.req = '1' then
t.consume := '1';
end if;
end if;
if mcwbo.grant = '1' then
v.active := '1';
v.mcwbi.req := '0';
v.mcwbi.data := r.data;
v.retry_mcwbi := r.mcwbi;
v.retry_mcwbi.data := r.data;
if t.req = '1' then
t.consume := '1';
end if;
end if;
if mcwbo.retry = '1' then
v.buf_mcwbi := r.mcwbi;
v.buf_mcwbi.data := r.data;
v.mcwbi := r.retry_mcwbi;
v.data := r.retry_mcwbi.data;
end if;
if t.consume = '1' then
if r.buf_mcwbi.req = '1' then
v.buf_mcwbi.req := '0';
v.data := r.buf_mcwbi.data;
v.mcwbi := r.buf_mcwbi;
else
if (wbfifoo.fifo_empty_r = '0') then
v.mcwbi.req := '1';
v.data := wbfifoo.fifo_entry.data;
v.mcwbi.address := wbfifoo.fifo_entry.addr;
v.mcwbi.burst := wbfifoo.fifo_entry.burst;
v.mcwbi.size := wbfifoo.fifo_entry.size;
v.mcwbi.read := wbfifoo.fifo_entry.read;
v.mcwbi.lock := wbfifoo.fifo_entry.lock;
t.wbfifoi.fifo_read := '1';
else
v.mcwbi.req := '1';
t.o.fifo_stored_v := '1';
t.wbfifoi.fifo_write := '0';
v.data := i.fifo_entry.data;
v.mcwbi.address := i.fifo_entry.addr;
v.mcwbi.burst := i.fifo_entry.burst;
v.mcwbi.size := i.fifo_entry.size;
v.mcwbi.read := i.fifo_entry.read;
v.mcwbi.lock := i.fifo_entry.lock;
end if;
end if;
end if;
if ( rst = '0' ) then
v.mcwbi.req := '0';
v.active := '0';
v.buf_mcwbi.req := '0';
end if;
c <= v;
wbfifoi <= t.wbfifoi;
o <= t.o;
mcwbi <= r.mcwbi;
vdbg := rdbg;
vdbg.dbg := t;
cdbg <= vdbg;
end process p0;
pregs : process (clk, c)
begin
if rising_edge(clk) then
r <= c;
rdbg <= cdbg;
end if;
end process;
gfifo0 : if CFG_WBBUF_SZ > 0 generate
fifo0 : genwbfifo generic map ( WBBUF_SZ => CFG_WBBUF_SZ )
port map (rst, clk, wbfifoi, wbfifoo );
end generate;
end rtl;
Type cache_config_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd
type cache_config_type is record
isets : integer range 1 to 4; isetsize : integer; ilinesize : integer; ireplace : cache_replace_type; ilock : integer; dsets : integer range 1 to 4; dsetsize : integer; dlinesize : integer; dreplace : cache_replace_type; dlock : integer; dsnoop : dsnoop_type; drfast : boolean; dwfast : boolean; dlram : boolean; dlramsize : integer; dlramaddr : integer; end record;
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Type genwb_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd
type genwb_type_out is record
fifo_stored_v : std_logic;
empty_v : std_logic;
read_finish_v : std_logic;
read_mexc : std_logic;
read_data : std_logic_vector(31 downto 0);
end record;
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Type ahbmst_mp_in defined in /tmp/build_html/vhdl/bus/bus_comp.vhd
type ahbmst_mp_in is record
req : std_logic;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : lmd_memsize;
burst : std_logic;
read : std_logic;
lock : std_logic;
end record;
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Type kecswb_reg_type defined in /tmp/build_html/vhdl/mem/cache/kecs_wb.vhd
type kecswb_reg_type is record
active : std_logic;
mcwbi : kbah_ketyp_in;
last_addr, last_data : std_logic_vector(31 downto 0);
end record;
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If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004
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This is part of the Core distribution