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[Donate]
library ieee;
use ieee.std_logic_1164.all;
use work.leon_target.all;
use work.leon_config.all;
use work.amba.all;
use work.ctrl_comp.all;
use work.corelib.all;
use work.core_comp.all;
use work.core_config.all;
use work.peri_io_comp.all;
use work.peri_mem_comp.all;
use work.arm_comp.all;
use work.bus_comp.all;
entity soc_gen is
generic (
ARCH_TYPE : cfg_core_types := cfg_core_arm );
port (
clk : in std_logic;
clkn : in std_logic;
rst : in std_logic;
ci : in cco_in;
co : out cco_out
);
end soc_gen;
architecture rtl of soc_gen is
signal ahbmi : ahb_mst_in_vector (0 to AHB_MST_MAX-1);
signal ahbmo : ahb_mst_out_vector(0 to AHB_MST_MAX-1);
signal apbi : apb_slv_in_vector (0 to APB_SLV_MAX-1);
signal apbo : apb_slv_out_vector(0 to APB_SLV_MAX-1);
signal ahbsi : ahb_slv_in_vector (0 to AHB_SLV_MAX-1);
signal ahbso : ahb_slv_out_vector(0 to AHB_SLV_MAX);
signal mctrl_apbi : apb_slv_in_type;
signal mctrl_apbo : apb_slv_out_type;
signal mctrl_ahbsi : ahb_slv_in_type;
signal mctrl_ahbso : ahb_slv_out_type;
signal mctrl_mctrlo: mctrl_out_type;
signal mctrl_pioo : pio_out_type;
signal mctrl_wpo : wprot_out_type;
signal mctrl_memo : memory_out_type;
signal mctrl_sdo : sdram_out_type;
signal mctrl_memi : memory_in_type;
signal apb_ahbsi : ahb_slv_in_type;
signal apb_ahbso : ahb_slv_out_type;
signal arm_apbi : apb_slv_in_type;
signal arm_apbo : apb_slv_out_type;
signal arm_ahbi : ahb_mst_in_type;
signal arm_ahbo : ahb_mst_out_type;
signal arm_i : arm_proc_typ_in;
signal arm_o : arm_proc_typ_out;
signal timo : timers_out_type;
signal irqi : irq_in_type;
signal irqo : irq_out_type;
signal irqi_iu : irq_iu_in_type;
signal irqo_iu : irq_iu_out_type;
signal irq2i : irq2_in_type;
signal irq2o : irq2_out_type;
begin
ahb0 : ahbarb generic map ( masters => AHB_MASTERS, defmast => AHB_DEFMST)
port map ( rst, clk, ahbmi(0 to AHB_MASTERS-1), ahbmo(0 to AHB_MASTERS-1), ahbsi, ahbso);
apb0 : apbmst port map (rst, clk, apb_ahbsi, apb_ahbso, apbi, apbo);
apb_ahbsi <= ahbsi(1);
ahbso(1) <= apb_ahbso;
socarm : if ( ARCH_TYPE = cfg_core_arm ) generate
arm0 : arm_proc port map (rst, clk, clkn, arm_i, arm_o, arm_ahbi, arm_ahbo, arm_apbi, arm_apbo );
arm_ahbi <= ahbmi(0);
ahbmo(0) <= arm_ahbo;
arm_apbi <= apbi(2);
apbo(2) <= arm_apbo;
irqi_iu <= arm_o.irqi;
arm_i.irqo <= irqo_iu;
end generate;
mctrl0 : mctrl port map (
rst => rst, clk=> clk, memi => mctrl_memi, memo => mctrl_memo,
ahbsi => mctrl_ahbsi, ahbso => mctrl_ahbso, apbi => mctrl_apbi, apbo => mctrl_apbo,
pioo => mctrl_pioo, wpo => mctrl_wpo, sdo => mctrl_sdo, mctrlo => mctrl_mctrlo
);
co.memo <= mctrl_memo;
mctrl_memi <= ci.memi;
co.sdo <= mctrl_sdo;
mctrl_ahbsi <= ahbsi(0);
ahbso(0) <= mctrl_ahbso;
mctrl_apbi <= apbi(0);
apbo(0) <= mctrl_apbo;
timers0 : timers
port map (rst => rst, clk => clk, apbi => apbi(5),
apbo => apbo(5), timo => timo);
irqctrl0 : irqctrl
port map (rst => rst, clk => clk, apbi => apbi(8),
apbo => apbo(8), irqi => irqi, irqo => irqo);
irqi.iu <= irqi_iu;
irqi.irq(15) <= '0';
irqi.irq(14) <= '0';
irqi.irq(13) <= '0';
irqi.irq(12) <= '0';
irqi.irq(11) <= '0';
irqi.irq(10) <= irq2o.irq when IRQ2EN else '0';
irqi.irq(9) <= timo.irq(1); irqi.irq(8) <= timo.irq(0); irqi.irq(7 downto 4) <= (others => '0'); irqi.irq(3) <= '0'; irqi.irq(2) <= '0'; irqi.irq(1) <= '0'; irqo_iu <= irqo.iu;
i2 : if CFG_CORE_IRQ2EN generate
irqctrl1 : irqctrl2
port map (rst => rst, clk => clk, apbi => apbi(10),
apbo => apbo(10), irqi => irq2i, irqo => irq2o);
end generate;
end rtl;
Type memory_out_type defined in /tmp/build_html/vhdl/peripherals/mem/peri_mem_comp.vhd
type memory_out_type is record
address : std_logic_vector(27 downto 0);
data : std_logic_vector(31 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
iosn : std_logic;
romsn : std_logic_vector(1 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
read : std_logic;
end record;
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Type sdram_out_type defined in /tmp/build_html/vhdl/peripherals/mem/peri_mem_comp.vhd
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); sdcsn : std_logic_vector ( 1 downto 0); sdwen : std_logic; rasn : std_logic; casn : std_logic; dqm : std_logic_vector ( 3 downto 0); end record;
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Type pio_out_type defined in /tmp/build_html/vhdl/peripherals/io/peri_io_comp.vhd
type pio_out_type is record
irq : std_logic_vector(3 downto 0);
piol : std_logic_vector(31 downto 0);
piodir : std_logic_vector(17 downto 0);
io8lsb : std_logic_vector(7 downto 0);
rxd : std_logic_vector(1 downto 0);
ctsn : std_logic_vector(1 downto 0);
wrio : std_logic;
end record;
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If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004
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This is part of the Core distribution
