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library ieee;
use ieee.std_logic_1164.all;
package armshiefter is
type ash_styp is (
ash_styp_none, ash_styp_immrot, ash_styp_simm, ash_styp_sreg );
type ash_sdir is (
ash_sdir_snone, ash_sdir_slsl, ash_sdir_slsr, ash_sdir_sasr, ash_sdir_sror, ash_sdir_srrx );
procedure aas_shieft(
insn : in std_logic_vector(31 downto 0);
dir : in ash_sdir;
typ : in ash_styp;
data1 : in std_logic_vector(31 downto 0);
data2 : in std_logic_vector(31 downto 0);
carry : in std_logic;
shieftout : out std_logic_vector(31 downto 0);
shieftcarryout : out std_logic
);
end armshiefter;
package body armshiefter is
constant ASH_DAPRAMxLDSTAM_IMMROT_U : integer := 11; constant ASH_DAPRAMxLDSTAM_IMMROT_D : integer := 8;
constant ASH_DAPRAMxLDSTAM_IMM_U : integer := 7; constant ASH_DAPRAMxLDSTAM_IMM_D : integer := 0;
constant ASH_DAPRAMxLDSTAM_SIMM_U : integer := 11; constant ASH_DAPRAMxLDSTAM_SIMM_D : integer := 7;
type shift_src is (shiftin_00,shiftin_32,shiftin_33,shiftin_prev);
procedure aas_shieft(
insn : in std_logic_vector(31 downto 0);
dir : in ash_sdir;
typ : in ash_styp;
data1 : in std_logic_vector(31 downto 0);
data2 : in std_logic_vector(31 downto 0);
carry : in std_logic;
shieftout : out std_logic_vector(31 downto 0);
shieftcarryout : out std_logic
) is
variable op1 : std_logic_vector(31 downto 0);
variable op2 : std_logic_vector(4 downto 0);
variable shiftin : std_logic_vector(64 downto 0);
variable carryout : std_logic;
variable carryoutsrc : shift_src;
begin
carryoutsrc := shiftin_prev;
carryout := carry;
op1 := data1;
op2 := (others => '0');
shiftin := (others => '0');
shiftin(32 downto 1) := data1;
case typ is
when ash_styp_immrot =>
op1 := (others => '0');
op1(7 downto 0) := insn(ASH_DAPRAMxLDSTAM_IMM_U downto ASH_DAPRAMxLDSTAM_IMM_D);
shiftin := (others => '0');
shiftin(32 downto 1) := op1;
shiftin(64 downto 33) := op1;
op2 := insn(ASH_DAPRAMxLDSTAM_IMMROT_U downto ASH_DAPRAMxLDSTAM_IMMROT_D) & "0";
carryoutsrc := shiftin_32;
if op2 = "00000" then carryoutsrc := shiftin_prev;
carryout := carry;
end if;
when ash_styp_simm =>
shiftin := (others => '0');
shiftin(32 downto 1) := data2;
case dir is
when ash_sdir_slsl =>
shiftin := (others => '0');
shiftin(64) := carry;
shiftin(63 downto 32) := data2;
op2 := not insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
carryoutsrc := shiftin_33;
when ash_sdir_slsr =>
shiftin := (others => '0');
shiftin(0) := carry;
shiftin(32 downto 1) := data2;
op2 := insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
carryoutsrc := shiftin_00;
when ash_sdir_sasr =>
if data2(31) = '1' then
shiftin(64 downto 33) := (others => '1');
else
shiftin(64 downto 33) := (others => '0');
end if;
shiftin(0) := carry;
shiftin(32 downto 1) := data2;
op2 := insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
if op2 = "00000" then
if data2(31) = '1' then
shiftin(32 downto 0) := (others => '1');
else
shiftin(32 downto 0) := (others => '0');
end if;
end if;
carryoutsrc := shiftin_00;
when ash_sdir_sror =>
shiftin := (others => '0');
shiftin(64 downto 33) := data2;
shiftin(32 downto 1) := data2;
op2 := insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
carryoutsrc := shiftin_32;
when ash_sdir_srrx =>
shiftin(31 downto 0) := data2;
shiftin(32) := carry;
op2 := (others => '0');
carryoutsrc := shiftin_00;
when ash_sdir_snone =>
op2 := (others => '0');
when others => null;
end case;
when ash_styp_sreg =>
shiftin := (others => '0');
shiftin(32 downto 1) := data1;
case dir is
when ash_sdir_slsl =>
shiftin := (others => '0');
shiftin(64) := carry;
shiftin(63 downto 32) := data1;
op2 := not data2(4 downto 0);
carryoutsrc := shiftin_33;
if not (data2(7 downto 5) = "000") then shiftin := (others => '0');
if data2(7 downto 0) = "00100000" then carryoutsrc := shiftin_prev;
carryout := data1(0);
end if;
end if;
when ash_sdir_slsr =>
shiftin := (others => '0');
shiftin(0) := carry;
shiftin(32 downto 1) := data1;
op2 := data2(4 downto 0);
carryoutsrc := shiftin_00;
if not (data2(7 downto 5) = "000") then shiftin := (others => '0');
if data2(7 downto 0) = "00100000" then carryoutsrc := shiftin_prev;
carryout := data1(31);
end if;
end if;
when ash_sdir_sasr =>
if data1(31) = '1' then
shiftin(64 downto 33) := (others => '1');
else
shiftin(64 downto 33) := (others => '0');
end if;
shiftin(0) := carry;
shiftin(32 downto 1) := data1;
op2 := data2(4 downto 0);
if not (data2(7 downto 5) = "000") then if data1(31) = '1' then
shiftin(32 downto 0) := (others => '1');
else
shiftin(32 downto 0) := (others => '0');
end if;
end if;
carryoutsrc := shiftin_00;
when ash_sdir_sror =>
shiftin := (others => '0');
shiftin(64 downto 33) := data1;
shiftin(32 downto 1) := data1;
op2 := data2(4 downto 0);
carryoutsrc := shiftin_32;
if data2(7 downto 0) = "00000000" then carryoutsrc := shiftin_prev;
carryout := carry;
end if;
when ash_sdir_srrx =>
op2 := (others => '0');
shiftin(31 downto 0) := carry & shiftin(31 downto 1);
when ash_sdir_snone =>
when others => null;
end case;
when ash_styp_none =>
shiftin := (others => '0');
shiftin(32 downto 1) := data2;
when others =>
end case;
if op2 (4) = '1' then
shiftin(48 downto 0) := shiftin(64 downto 16);
end if;
if op2 (3) = '1' then
shiftin(40 downto 0) := shiftin(48 downto 8);
end if;
if op2 (2) = '1' then
shiftin(36 downto 0) := shiftin(40 downto 4);
end if;
if op2 (1) = '1' then
shiftin(34 downto 0) := shiftin(36 downto 2);
end if;
if op2 (0) = '1' then
shiftin(32 downto 0) := shiftin(33 downto 1);
end if;
case carryoutsrc is
when shiftin_00 => carryout := shiftin(0);
when shiftin_33 => carryout := shiftin(33);
when shiftin_32 => carryout := shiftin(32);
when shiftin_prev =>
when others => null;
end case;
shieftout := shiftin(32 downto 1);
shieftcarryout := carryout;
end;
end armshiefter;
Procedure aas_shieft defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd
procedure aas_shieft(
insn : in std_logic_vector(31 downto 0);
dir : in ash_sdir;
typ : in ash_styp;
data1 : in std_logic_vector(31 downto 0);
data2 : in std_logic_vector(31 downto 0);
carry : in std_logic;
shieftout : out std_logic_vector(31 downto 0);
shieftcarryout : out std_logic
);
end armshiefter;
package body armshiefter is
constant ASH_DAPRAMxLDSTAM_IMMROT_U : integer := 11; constant ASH_DAPRAMxLDSTAM_IMMROT_D : integer := 8;
constant ASH_DAPRAMxLDSTAM_IMM_U : integer := 7; constant ASH_DAPRAMxLDSTAM_IMM_D : integer := 0;
constant ASH_DAPRAMxLDSTAM_SIMM_U : integer := 11; constant ASH_DAPRAMxLDSTAM_SIMM_D : integer := 7;
type shift_src is (shiftin_00,shiftin_32,shiftin_33,shiftin_prev);
procedure aas_shieft(
insn : in std_logic_vector(31 downto 0);
dir : in ash_sdir;
typ : in ash_styp;
data1 : in std_logic_vector(31 downto 0);
data2 : in std_logic_vector(31 downto 0);
carry : in std_logic;
shieftout : out std_logic_vector(31 downto 0);
shieftcarryout : out std_logic
) is
variable op1 : std_logic_vector(31 downto 0);
variable op2 : std_logic_vector(4 downto 0);
variable shiftin : std_logic_vector(64 downto 0);
variable carryout : std_logic;
variable carryoutsrc : shift_src;
begin
carryoutsrc := shiftin_prev;
carryout := carry;
op1 := data1;
op2 := (others => '0');
shiftin := (others => '0');
shiftin(32 downto 1) := data1;
case typ is
when ash_styp_immrot =>
op1 := (others => '0');
op1(7 downto 0) := insn(ASH_DAPRAMxLDSTAM_IMM_U downto ASH_DAPRAMxLDSTAM_IMM_D);
shiftin := (others => '0');
shiftin(32 downto 1) := op1;
shiftin(64 downto 33) := op1;
op2 := insn(ASH_DAPRAMxLDSTAM_IMMROT_U downto ASH_DAPRAMxLDSTAM_IMMROT_D) & "0";
carryoutsrc := shiftin_32;
if op2 = "00000" then carryoutsrc := shiftin_prev;
carryout := carry;
end if;
when ash_styp_simm =>
shiftin := (others => '0');
shiftin(32 downto 1) := data2;
case dir is
when ash_sdir_slsl =>
shiftin := (others => '0');
shiftin(64) := carry;
shiftin(63 downto 32) := data2;
op2 := not insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
carryoutsrc := shiftin_33;
when ash_sdir_slsr =>
shiftin := (others => '0');
shiftin(0) := carry;
shiftin(32 downto 1) := data2;
op2 := insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
carryoutsrc := shiftin_00;
when ash_sdir_sasr =>
if data2(31) = '1' then
shiftin(64 downto 33) := (others => '1');
else
shiftin(64 downto 33) := (others => '0');
end if;
shiftin(0) := carry;
shiftin(32 downto 1) := data2;
op2 := insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
if op2 = "00000" then
if data2(31) = '1' then
shiftin(32 downto 0) := (others => '1');
else
shiftin(32 downto 0) := (others => '0');
end if;
end if;
carryoutsrc := shiftin_00;
when ash_sdir_sror =>
shiftin := (others => '0');
shiftin(64 downto 33) := data2;
shiftin(32 downto 1) := data2;
op2 := insn(ASH_DAPRAMxLDSTAM_SIMM_U downto ASH_DAPRAMxLDSTAM_SIMM_D);
carryoutsrc := shiftin_32;
when ash_sdir_srrx =>
shiftin(31 downto 0) := data2;
shiftin(32) := carry;
op2 := (others => '0');
carryoutsrc := shiftin_00;
when ash_sdir_snone =>
op2 := (others => '0');
when others => null;
end case;
when ash_styp_sreg =>
shiftin := (others => '0');
shiftin(32 downto 1) := data1;
case dir is
when ash_sdir_slsl =>
shiftin := (others => '0');
shiftin(64) := carry;
shiftin(63 downto 32) := data1;
op2 := not data2(4 downto 0);
carryoutsrc := shiftin_33;
if not (data2(7 downto 5) = "000") then shiftin := (others => '0');
if data2(7 downto 0) = "00100000" then carryoutsrc := shiftin_prev;
carryout := data1(0);
end if;
end if;
when ash_sdir_slsr =>
shiftin := (others => '0');
shiftin(0) := carry;
shiftin(32 downto 1) := data1;
op2 := data2(4 downto 0);
carryoutsrc := shiftin_00;
if not (data2(7 downto 5) = "000") then shiftin := (others => '0');
if data2(7 downto 0) = "00100000" then carryoutsrc := shiftin_prev;
carryout := data1(31);
end if;
end if;
when ash_sdir_sasr =>
if data1(31) = '1' then
shiftin(64 downto 33) := (others => '1');
else
shiftin(64 downto 33) := (others => '0');
end if;
shiftin(0) := carry;
shiftin(32 downto 1) := data1;
op2 := data2(4 downto 0);
if not (data2(7 downto 5) = "000") then if data1(31) = '1' then
shiftin(32 downto 0) := (others => '1');
else
shiftin(32 downto 0) := (others => '0');
end if;
end if;
carryoutsrc := shiftin_00;
when ash_sdir_sror =>
shiftin := (others => '0');
shiftin(64 downto 33) := data1;
shiftin(32 downto 1) := data1;
op2 := data2(4 downto 0);
carryoutsrc := shiftin_32;
if data2(7 downto 0) = "00000000" then carryoutsrc := shiftin_prev;
carryout := carry;
end if;
when ash_sdir_srrx =>
op2 := (others => '0');
shiftin(31 downto 0) := carry & shiftin(31 downto 1);
when ash_sdir_snone =>
when others => null;
end case;
when ash_styp_none =>
shiftin := (others => '0');
shiftin(32 downto 1) := data2;
when others =>
end case;
if op2 (4) = '1' then
shiftin(48 downto 0) := shiftin(64 downto 16);
end if;
if op2 (3) = '1' then
shiftin(40 downto 0) := shiftin(48 downto 8);
end if;
if op2 (2) = '1' then
shiftin(36 downto 0) := shiftin(40 downto 4);
end if;
if op2 (1) = '1' then
shiftin(34 downto 0) := shiftin(36 downto 2);
end if;
if op2 (0) = '1' then
shiftin(32 downto 0) := shiftin(33 downto 1);
end if;
case carryoutsrc is
when shiftin_00 => carryout := shiftin(0);
when shiftin_33 => carryout := shiftin(33);
when shiftin_32 => carryout := shiftin(32);
when shiftin_prev =>
when others => null;
end case;
shieftout := shiftin(32 downto 1);
shieftcarryout := carryout;
end;
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If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004
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This is part of the Core distribution