type astates is (idle, dcache, icache, mmu);

type rdatatype is (itag, idata, memory);

type cli_hold is record
   hold : std_logic; -- hold
   dhold : std_logic; -- dcache hold
   ihold : std_logic; -- icache hold
end record;

type mcycletype is (midle, active, leadout);

constant zero : std_logic_vector(31 downto 0) := (others =>

type apm_excpsr is record
   n      : std_logic;                  -- negative
   z      : std_logic;                  -- zero
   c      : std_logic;                  -- carry
   v      : std_logic;                  -- overflow
   -- extensions
   -- fext   : std_logic_vector(3 downto 0);  -- cpsr(27:24)
   -- xext   : std_logic_vector(7 downto 0);  -- cpsr(15:8)
   -- sext   : std_logic_vector(7 downto 0);  -- cpsr(23:16)
end record;

type apm_wrcpsr is record
   i      : std_logic;                  -- [7] irq
   f      : std_logic;                  -- [6] fiq
   t      : std_logic;                  -- [5] thumb
   mode   : std_logic_vector(4 downto 0);
-- pragma translate_off
--   dbgmode  : aba_atyp_dbgpmode;       -- readable pmode for dbg
-- pragma translate_on
end record;

type apm_cpsr is record
   ex : apm_excpsr;
   wr : apm_wrcpsr;
end record;

type ade_insntyp is (
  ade_typmem,
  ade_typalu,
  ade_typmisc,
  ade_typcp
);

type ade_decinsn is (
  type_arm_invalid,type_arm_nop,    type_arm_mrs,    type_arm_bx,    type_arm_mul,   type_arm_mla,
  type_arm_swp,    type_arm_sumull, type_arm_sumlal, type_arm_strhb, type_arm_ldrhb, type_arm_and,
  type_arm_sub,    type_arm_eor,    type_arm_rsb,    type_arm_add,   type_arm_sbc,   type_arm_adc, 
  type_arm_msr,    type_arm_teq,    type_arm_cmn,    type_arm_tst,   type_arm_cmp,   type_arm_orr, 
  type_arm_mov,    type_arm_mvn,    type_arm_str1,   type_arm_str2,  type_arm_str3,  type_arm_ldr1,
  type_arm_stm,    type_arm_ldm,    type_arm_b,      type_arm_swi,   type_arm_cdp,   type_arm_mrc,
  type_arm_mcr,    type_arm_stc,    type_arm_ldc,    type_arm_rsc,   type_arm_bic,   type_arm_undefined
);

type ade_DAPRAM is (
  ade_DAPRAM_simm,       -- OP2 shieft with imm 
  ade_DAPRAM_sreg,       -- OP2 shieft with reg 
  ade_DAPRAM_immrot      -- OP2 immidiate rotated
);

type ade_LDSTAMxLSV4AM is (
  ade_LDSTAMxLSV4AM_imm,  -- addr v1 imm
                          -- addr v4 imm
  ade_LDSTAMxLSV4AM_reg   -- addr v1 reg (shieft with imm)
                          -- addr v4 reg
);

type icycletype is (iidle, pre, ref1, ref2, lmode, finish);

type ade_pos is (
  ade_pre,      -- pre indexed
  ade_post      -- post indexed
);

type ash_sdir is (
  ash_sdir_snone,    -- no shieft
  ash_sdir_slsl,     -- LSL #: logical shieft left 
  ash_sdir_slsr,     -- LSR #: logical shieft righ
  ash_sdir_sasr,     -- ASR #: arithmetic shieft left
  ash_sdir_sror,     -- ROR #: rotate 
  ash_sdir_srrx      -- RRX #: rotate 1 with carry
);

type ade_amode is record
  DAPRAM_typ           : ade_DAPRAM;
  LDSTAM_typ           : ade_LDSTAMxLSV4AM;
  LSV4AM_typ           : ade_LDSTAMxLSV4AM;
  LDSTAMxLSV4AM_pos    : ade_pos;
  DAPRAMxLDSTAM_sdir   : ash_sdir;
  LDSTAMxLSV4AM_uacc   : std_logic;
  LDSTAMxLSV4AM_wb     : std_logic;
end record;

type ade_insn is record
  pc_8    : std_logic_vector(31 downto 0);
  insn    : std_logic_vector(31 downto 0);
  insntyp : ade_insntyp;
  decinsn : ade_decinsn;
  am      : ade_amode;
  valid   : std_logic;
  id      : std_logic_vector(2 downto 0);
end record;

type apc_rrstg is record
  -- operations
  dummy : std_logic;
end record;

type apc_rsop_opsrc is (
  apc_opsrc_through,
  apc_opsrc_buf,
  apc_opsrc_alures,
  apc_opsrc_none
);

type apc_rsop_bufsrc is (
  apc_bufsrc_none,
  apc_bufsrc_through,
  apc_bufsrc_alures
);

type ash_styp is (
  ash_styp_none,  -- no shieft
  ash_styp_immrot,-- DAPRAM: OP2 immidiate rotated
  ash_styp_simm,  -- DAPRAM: OP2 shieft with imm, LDSTAM: addr v1 reg (adm_LDSTAM_reg) 
  ash_styp_sreg   -- DAPRAM: OP2 shieft with reg  
);

type txfsmtype is (idle, data, stopbit);

type apc_rsstg is record
  -- operations
  rsop_op1_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_op2_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source
  rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source
  rsop_styp     : ash_styp;        -- RSSTG shieft op
  rsop_sdir     : ash_sdir;        -- RSSTG shieft dir
  -- data
  rs_shieftcarryout : std_logic;   -- RSSTG shiefter carry out
end record;

type apc_exop_datasrc is (
  apc_datasrc_aluout,
  apc_datasrc_buf,
  apc_datasrc_none
);

type apc_exop_bufsrc is (
  apc_exbufsrc_none,
  apc_exbufsrc_aluout,
  apc_exbufsrc_op1
);

type cpins_type is (none, cpop, load, store);

type apc_exstg is record
  -- operations
  exop_aluop    : std_logic_vector(3 downto 0);  -- EXSTG alu operation
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source
  exop_setcpsr  : std_logic;         -- EXSTG set cpsr
  -- data                                   
  ex_cpsr : apm_cpsr;           -- EXSTG store old cpsr
end record;

type apc_dmstg is record
  dummy : std_logic;
end record;

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

type apc_mestg is record
  -- operation
  meop_enable : std_logic;
  meop_param  : gdcl_param;
  -- data
  mexc   : std_logic;
end record;

constant APM_RREAL_U : integer := 4;

constant APM_RREAL_D : integer := 0;

type slavestate is (idle, error, split, retry, ws1);

type dsnoop_type is (none, slow, fast);

type apm_trap is (
  apm_trap_reset,   -- reset
  apm_trap_undef,   -- undefined (EXSTG)
  apm_trap_swi,     -- software interrupt (DRSTG)
  apm_trap_prefch,  -- prefetch error (IMSTG)
  apm_trap_dabort,  -- data abort error (MESTG)
  apm_trap_irq,     -- interrupt
  apm_trap_fiq      -- fast interrupt
);

type apm_trapctrl is record
  traptype : apm_trap;
  trap     : std_logic;
end record;

type apc_wrstg is record
  -- operation
  wrop_rd      : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  wrop_rdvalid : std_logic;
  wrop_setspsr : std_logic;
  wrop_trap    : apm_trapctrl;
end record;

type apc_pctrl is record
  insn : ade_insn;
  valid : std_logic;
  rr : apc_rrstg;
  rs : apc_rsstg;
  ex : apc_exstg;
  dm : apc_dmstg;
  me : apc_mestg;
  wr : apc_wrstg;
  data1 : std_logic_vector(31 downto 0);
  data2 : std_logic_vector(31 downto 0);
end record;

type apc_pstate is record
  hold_r    : cli_hold;
  nextinsn_v : std_logic;
  dabort_v : std_logic;
  -- active cpsr
  fromEX_cpsr_r : apm_cpsr;
  -- pctrls of all stages from rrstg on 
  fromRR_pctrl_r : apc_pctrl;
  fromRS_pctrl_r : apc_pctrl;
  fromEX_pctrl_r : apc_pctrl;
  fromDM_pctrl_r : apc_pctrl;
  fromME_pctrl_r : apc_pctrl;
  fromWR_pctrl_r : apc_pctrl;
end record;

type gendc_type_out is record
  wr_data : std_logic_vector(31 downto 0);
  me_mexc : std_logic;
  wr_mexc : std_logic;
  hold : std_logic;
end record;

type armiu_wrstg_typ_in is record
   pstate : apc_pstate;
   fromME_pctrl_v : apc_pctrl;
   dco   : gendc_type_out;
   
   fromCP_data : std_logic_vector(31 downto 0);
end record;

type apm_spsr is record
    svc_spsr : apm_cpsr;    
    abt_spsr : apm_cpsr;  
    und_spsr : apm_cpsr;   
    irq_spsr : apm_cpsr;   
    fiq_spsr : apm_cpsr;
end record;

type irq_iu_in_type is record
  intack	: std_logic;                      -- interrupt acknoledge (clear i.irl bit)
  irl		: std_logic_vector(3 downto 0);   
end record;

type armiu_wrstg_typ_out is record
   pctrl_r : apc_pctrl;

   spsr_r : apm_spsr;

   irqi : irq_iu_in_type;
   
   toIM_branch_v : std_logic;
   toIM_branchaddr_v : std_logic_vector(31 downto 0);
   
   toDR_dabort_v : std_logic;

   toEX_cpsr_v : apm_cpsr;
   toEX_cpsrset_v : std_logic;

   toRR_rd_v : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
   toRR_rd_valid_v : std_logic;
   toRR_rd_data_v : std_logic_vector(31 downto 0);
   
   toCPWR_crd_data_v : std_logic_vector(31 downto 0);
end record;

type armiu_wrstg_tmp_type is record
    o       : armiu_wrstg_typ_out;
    trap : apm_trapctrl;
    oldcpsr : apm_cpsr;
    newcpsr : apm_cpsr;
    oldspsr : apm_cpsr;
    newspsr : apm_cpsr;
    setspsr_mode : std_logic_vector(4 downto 0);
    spsr : apm_spsr;
    irqi_intack : std_logic;
  end record;

type armiu_wrstg_reg_type is record
    pctrl : apc_pctrl;
    spsr : apm_spsr;
  end record;

type armiu_wrstg_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_wrstg_tmp_type;
     -- pragma translate_on
  end record;

constant APM_SVC : std_logic_vector(4 downto 0) := "10011";

constant APM_ABT : std_logic_vector(4 downto 0) := "10111";

constant APM_UND : std_logic_vector(4 downto 0) := "11011";

constant APM_IRQ : std_logic_vector(4 downto 0) := "10010";

constant APM_FIQ : std_logic_vector(4 downto 0) := "10001";

function apm_bankspsr(
  mode : in  std_logic_vector(4 downto 0);
  spsr : in  apm_spsr
) return apm_cpsr is
variable tmp : apm_cpsr;
begin
  tmp := spsr.svc_spsr;
  case mode is
    when APM_SVC =>
      tmp := spsr.svc_spsr;
    when APM_ABT => 
      tmp := spsr.abt_spsr;
    when APM_UND => 
      tmp := spsr.und_spsr;
    when APM_IRQ => 
      tmp := spsr.irq_spsr;
    when APM_FIQ => 
      tmp := spsr.fiq_spsr;
    when others => 
  end case;
  return tmp;
end;

constant APM_RREAL_PC : std_logic_vector(4 downto 0) := "01111";

function apc_is_branch(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.wr.wrop_rdvalid = '1') and
       (pctrl.wr.wrop_rd = APM_RREAL_PC) then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_straddr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.me.meop_enable = '1') and
       (pctrl.me.meop_param.read = '0') and
       (pctrl.me.meop_param.addrin = '1') then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_strdata(
  pctrl   : apc_pctrl
) return boolean  is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.me.meop_enable = '1') and
       (pctrl.me.meop_param.read = '0') and
       (pctrl.me.meop_param.writedata = '1') then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_rdlocked(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) and
     (pctrl.me.meop_enable = '1') and
     (pctrl.me.meop_param.read = '1') and
     (pctrl.wr.wrop_rdvalid = '1') then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_rdlocked_by (
  rd    : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  pctrl : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if (pctrl.wr.wrop_rd = rd) and apc_is_rdlocked(pctrl) then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_rdfromalu(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if  apc_is_valid(pctrl) and
     (not apc_is_memload(pctrl)) and 
     (pctrl.wr.wrop_rdvalid = '1') then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_rswillshieft(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    -- shiefter output used
    if pctrl.rs.rsop_op2_src = apc_opsrc_through or
       pctrl.rs.rsop_buf2_src = apc_bufsrc_through then
      -- shiefter does something
      if (pctrl.rs.rsop_styp = ash_styp_simm) or
         (pctrl.rs.rsop_styp = ash_styp_sreg) then
        if not (pctrl.rs.rsop_sdir = ash_sdir_snone) then
          tmp := true;
        end if;
      end if;
    end if;
  end if;
  return tmp;
end;

function apc_is_exwillsetcpsr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := apc_is_valid(pctrl) and
        (pctrl.ex.exop_setcpsr = '1') ;
  return tmp;
end;

function apc_is_usecpsr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if apc_is_rswillshieft(pctrl) then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);

function apc_is_flush(
  stgid : std_logic_vector(2 downto 0);
  flushid : std_logic_vector(2 downto 0)
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if not (stgid = flushid) then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_valid (
  pctrl : apc_pctrl
) return boolean;

-- check weather branch (reg/mem)
function apc_is_branch(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------
-- pctrl predicate: mem op 

-- check weather mestg active
function apc_is_mem(
  pctrl   : apc_pctrl
) return boolean;

-- check weather mestg load
function apc_is_memload(
  pctrl   : apc_pctrl
) return boolean;

-- check weather str addr (next pctrl will be store data) 
function apc_is_straddr(
  pctrl   : apc_pctrl
) return boolean;

-- check weather str data (prev pctrl was be store addr) 
function apc_is_strdata(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------
-- pctrl predicate: register locking 

-- check weather it is a mem ldr
function apc_is_rdlocked(
  pctrl   : apc_pctrl
) return boolean;

-- check weather app_is_rdlocked() + rd compare
function apc_is_rdlocked_by (
  rd    : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  pctrl : apc_pctrl
) return boolean;

-- check weather wrstg rd data come from alu
function apc_is_rdfromalu(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------
-- pctrl predicate: cpsr locking 

-- check weather rsstg is used
function apc_is_rswillshieft(
  pctrl   : apc_pctrl
) return boolean;

-- check weather cpsr will be modified 
function apc_is_exwillsetcpsr(
  pctrl   : apc_pctrl
) return boolean;

-- check weather cpsr is used 
function apc_is_usecpsr(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------

-- check weather stg should flush
function apc_is_flush(
  stgid : std_logic_vector(2 downto 0);
  flushid : std_logic_vector(2 downto 0)
) return boolean;

end armpctrl;

package body armpctrl is

function apc_is_valid (
  pctrl : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if pctrl.valid = '1' then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_mem(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if pctrl.me.meop_enable = '1' then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_memload(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_mem(pctrl) then
    if pctrl.me.meop_param.read = '1' then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

type execstate is (nominal, excpend, exception);

constant APM_USR : std_logic_vector(4 downto 0) := "10000";

constant APM_SYS : std_logic_vector(4 downto 0) := "11111";

function apm_is_hasspsr (
  mode : std_logic_vector(4 downto 0)
) return boolean is
  variable tmp : boolean;
begin
  tmp := true;
  if mode = APM_USR or
     mode = APM_SYS then
    tmp := false;
  end if;
  return tmp;
end;

function apm_msr (
  insn : std_logic_vector(31 downto 0);
  newcpsr : apm_cpsr;
  oldcpsr : apm_cpsr
) return apm_cpsr is
  variable tmp : apm_cpsr;
begin
  tmp := oldcpsr;

  -- +---+---+---+---+---+------------+---+---+---+------+
  -- | n | z | c | v | q |   dnm(raz) | i | f | t | mode |
  -- +---+---+---+---+---+------------+---+---+---+------+

  -- $(del)
  -- if opcode[25] == 1
  --   operand = 8_bit_immediate Rotate_Right (rotate_imm * 2)
  -- else /* opcode[25] == 0 */
  --   operand = Rm
  --
  -- if R == 0 then
  --   if field_mask[0] == 1 and InAPrivilegedMode() then
  --   CPSR[7:0] = operand[7:0]
  --   if field_mask[1] == 1 and InAPrivilegedMode() then
  --   CPSR[15:8] = operand[15:8]
  --   if field_mask[2] == 1 and InAPrivilegedMode() then
  --   CPSR[23:16] = operand[23:16]
  --   if field_mask[3] == 1 then
  --   CPSR[31:24] = operand[31:24]
  -- else /* R == 1 */
  --   if field_mask[0] == 1 and CurrentModeHasSPSR() then
  --   SPSR[7:0] = operand[7:0]
  --   if field_mask[1] == 1 and CurrentModeHasSPSR() then
  --   SPSR[15:8] = operand[15:8]
  --   if field_mask[2] == 1 and CurrentModeHasSPSR() then
  --   SPSR[23:16] = operand[23:16]
  --   if field_mask[3] == 1 and CurrentModeHasSPSR() then
  --   SPSR[31:24] = operand[31:24]
  -- $(/del)

  
  if insn(APM_MSR_C) = '1' then
    tmp.wr.i := newcpsr.wr.i;
    tmp.wr.f := newcpsr.wr.f;
    tmp.wr.t := newcpsr.wr.t;
    tmp.wr.mode := newcpsr.wr.mode;
  end if;
  if insn(APM_MSR_X) = '1' then
    -- extensions
    -- tmp.xext := newcpsr.xext;
  end if;
  if insn(APM_MSR_S) = '1' then
    -- extensions
    -- tmp.sext := newcpsr.sext;
  end if;
  if insn(APM_MSR_F) = '1' then
    tmp.ex.n := newcpsr.ex.n;
    tmp.ex.z := newcpsr.ex.z;
    tmp.ex.c := newcpsr.ex.c;
    tmp.ex.v := newcpsr.ex.v;
    -- extensions
    -- tmp.ex.fext := newcpsr.fext;
  end if;
  
  return tmp;
end;

constant APM_N_C : integer := 31;

constant APM_Z_C : integer := 30;

constant APM_C_C : integer := 29;

constant APM_V_C : integer := 28;

constant APM_I_C : integer := 7;

constant APM_F_C : integer := 6;

constant APM_T_C : integer := 5;

constant APM_MODE_U : integer := 4;

constant APM_MODE_D : integer := 0;

function apm_stdtocpsr (
  data : std_logic_vector
) return apm_cpsr is
  variable tmp : apm_cpsr;
begin
  
  tmp.ex.n := data(APM_N_C);
  tmp.ex.z := data(APM_Z_C);
  tmp.ex.c := data(APM_C_C);
  tmp.ex.v := data(APM_V_C);

  tmp.wr.i := data(APM_I_C);
  tmp.wr.f := data(APM_F_C);
  tmp.wr.t := data(APM_T_C);
  tmp.wr.mode := data(APM_MODE_U downto APM_MODE_D);

  -- extensions
  -- tmp.fext := data(ACP_FEXT_U downto ACP_FEXT_D);
  -- tmp.xext := data(ACP_XEXT_U downto ACP_XEXT_D);
  -- tmp.sext := data(ACP_SEXT_U downto ACP_SEXT_D);
  
  return tmp;
end;

constant APM_RESET_VEC  : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";

constant APM_UNDEF_VEC  : std_logic_vector(31 downto 0) := "00000000000000000000000000000100";

constant APM_SWI_VEC    : std_logic_vector(31 downto 0) := "00000000000000000000000000001000";

constant APM_PREFCH_VEC : std_logic_vector(31 downto 0) := "00000000000000000000000000001100";

constant APM_DABORT_VEC : std_logic_vector(31 downto 0) := "00000000000000000000000000010000";

constant APM_IRQ_VEC    : std_logic_vector(31 downto 0) := "00000000000000000000000000011000";

constant APM_FIQ_VEC    : std_logic_vector(31 downto 0) := "00000000000000000000000000011100";

function apm_cpsrtostd (
  cpsr : apm_cpsr
) return std_logic_vector is
  variable tmp : std_logic_vector(31 downto 0);
begin
  tmp := (others => '0');
  
  tmp(APM_N_C) := cpsr.ex.n;
  tmp(APM_Z_C) := cpsr.ex.z;
  tmp(APM_C_C) := cpsr.ex.c;
  tmp(APM_V_C) := cpsr.ex.v;
  tmp(APM_Q_C) := '0';

  tmp(APM_I_C) := cpsr.wr.i;
  tmp(APM_F_C) := cpsr.wr.f;
  tmp(APM_T_C) := cpsr.wr.t;
  
  tmp(APM_MODE_U downto APM_MODE_D) := cpsr.wr.mode;        

  -- extensions
  -- tmp(ACP_FEXT_U downto ACP_FEXT_D) := cpsr.fext;
  -- tmp(ACP_XEXT_U downto ACP_XEXT_D) := cpsr.xext;
  -- tmp(ACP_SEXT_U downto ACP_SEXT_D) := cpsr.sext;
  
  return tmp;
end;

constant APM_MSR_C : integer := 16;

constant APM_MSR_X : integer := 17;

constant APM_MSR_S : integer := 18;

constant APM_MSR_F : integer := 19;

constant APM_REG_U : integer := 3;

constant APM_REG_D : integer := 0;

constant APM_REG_LINK   : std_logic_vector(3 downto 0) := "1110";

constant APM_REG_PC     : std_logic_vector(3 downto 0) := "1111";

constant APM_REGLIST_SZ : integer := 16;

constant APM_REGLIST_pc : integer := 15;

function apm_bankreg(
  mode : in std_logic_vector(4 downto 0);
  addr : in std_logic_vector
) return std_logic_vector is
variable tmp  : std_logic_vector(addr'high+1 downto 0);  -- +1: return is 5bits
variable bank : std_logic_vector(addr'high+1 downto 0);  
begin
  tmp := "0"&addr(addr'high downto 0);
  bank := "0"&addr(addr'high downto 0);
  case mode is
    when APM_USR => 
    when APM_SYS => 
    when APM_SVC =>
      bank := "1100" & not addr(0);
    when APM_ABT => 
      bank := "1101" & not addr(0);
    when APM_UND => 
      bank := "1110" & not addr(0);
    when APM_FIQ => 
      if addr(3) = '1' then
        bank(4 downto 3) := "10";
        tmp(4 downto 3) := "10";
      end if;
    when APM_IRQ => 
      bank := "1111" & not addr(0);
    when others => 
  end case;
  case addr(3 downto 0) is
    when "1101"|"1110" => tmp := bank;
    when others => 
  end case;
  return tmp;
end;

function apm_is_privmode (
  mode : std_logic_vector(4 downto 0)
) return boolean;

-------------------------------------------------------------------------------

-- Trap types
type apm_trap is (
  apm_trap_reset,   -- reset
  apm_trap_undef,   -- undefined (EXSTG)
  apm_trap_swi,     -- software interrupt (DRSTG)
  apm_trap_prefch,  -- prefetch error (IMSTG)
  apm_trap_dabort,  -- data abort error (MESTG)
  apm_trap_irq,     -- interrupt
  apm_trap_fiq      -- fast interrupt
);

-- Trap jump vectors
constant APM_RESET_VEC  : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant APM_UNDEF_VEC  : std_logic_vector(31 downto 0) := "00000000000000000000000000000100";
constant APM_SWI_VEC    : std_logic_vector(31 downto 0) := "00000000000000000000000000001000";
constant APM_PREFCH_VEC : std_logic_vector(31 downto 0) := "00000000000000000000000000001100";
constant APM_DABORT_VEC : std_logic_vector(31 downto 0) := "00000000000000000000000000010000";
constant APM_IRQ_VEC    : std_logic_vector(31 downto 0) := "00000000000000000000000000011000";
constant APM_FIQ_VEC    : std_logic_vector(31 downto 0) := "00000000000000000000000000011100";

-- Trap ctrl
type apm_trapctrl is record
  traptype : apm_trap;
  trap     : std_logic;
end record;

-------------------------------------------------------------------------------

-- Current Program Status Register (CPSR)
-- +---+---+---+---+---+------------+---+---+---+------+
-- | n | z | c | v | q |   dnm(raz) | i | f | t | mode |
-- +---+---+---+---+---+------------+---+---+---+------+
-- exstg controlled part of CPSR
type apm_excpsr is record
   n      : std_logic;                  -- negative
   z      : std_logic;                  -- zero
   c      : std_logic;                  -- carry
   v      : std_logic;                  -- overflow
   -- extensions
   -- fext   : std_logic_vector(3 downto 0);  -- cpsr(27:24)
   -- xext   : std_logic_vector(7 downto 0);  -- cpsr(15:8)
   -- sext   : std_logic_vector(7 downto 0);  -- cpsr(23:16)
end record;
-- wrstg controlled part of CPSR
type apm_wrcpsr is record
   i      : std_logic;                  -- [7] irq
   f      : std_logic;                  -- [6] fiq
   t      : std_logic;                  -- [5] thumb
   mode   : std_logic_vector(4 downto 0);
-- pragma translate_off
--   dbgmode  : aba_atyp_dbgpmode;       -- readable pmode for dbg
-- pragma translate_on
end record;
-- complete CPSR
type apm_cpsr is record
   ex : apm_excpsr;
   wr : apm_wrcpsr;
end record;

-- Banked SPSR
type apm_spsr is record
    svc_spsr : apm_cpsr;    
    abt_spsr : apm_cpsr;  
    und_spsr : apm_cpsr;   
    irq_spsr : apm_cpsr;   
    fiq_spsr : apm_cpsr;
end record;

-- convert from stdlogic to spm_cpsr
function apm_stdtocpsr (
  data : std_logic_vector
) return apm_cpsr;

-- convert from spm_cpsr to stdlogic
function apm_cpsrtostd (
  cpsr : apm_cpsr
) return std_logic_vector;

-- assemble new cpsr for msr cmd
function apm_msr (
  insn : std_logic_vector(31 downto 0);
  newcpsr : apm_cpsr;
  oldcpsr : apm_cpsr
) return apm_cpsr;

constant APM_MSR_C : integer := 16;
constant APM_MSR_X : integer := 17;
constant APM_MSR_S : integer := 18;
constant APM_MSR_F : integer := 19;

-------------------------------------------------------------------------------
  
constant APM_RREAL_U : integer := 4; -- banked register range
constant APM_RREAL_D : integer := 0;
constant APM_REG_U : integer := 3;   -- logical register range
constant APM_REG_D : integer := 0;
constant APM_REG_LINK   : std_logic_vector(3 downto 0) := "1110";   -- link register
constant APM_REG_PC     : std_logic_vector(3 downto 0) := "1111";   -- programm counter
constant APM_RREAL_PC : std_logic_vector(4 downto 0) := "01111";  -- banked program counter

constant APM_REGLIST_SZ : integer := 16;
constant APM_REGLIST_pc : integer := 15;

-------------------------------------------------------------------------------

-- map to banked register of <mode>
function apm_bankreg(
  mode : in std_logic_vector(4 downto 0);
  addr : in std_logic_vector
) return std_logic_vector;

-- retrieve the banked spsr for <mode> 
function apm_bankspsr(
  mode : in  std_logic_vector(4 downto 0);
  spsr : in  apm_spsr
) return apm_cpsr;

-- set bank spsr
procedure apm_setspsr(
  mode : in  std_logic_vector(4 downto 0);
  spsr : inout  apm_spsr;
  cpsr : in  apm_cpsr
);

-- check weather <mode> has a spsr
function apm_is_hasspsr (
  mode : std_logic_vector(4 downto 0)
) return boolean;

end armpmodel;

package body armpmodel is

-------------------------------------------------------------------------------
  
function apm_is_privmode (
  mode : std_logic_vector(4 downto 0)
) return boolean is
  variable tmp : boolean;
begin
  tmp := true;
  if mode = APM_USR then
    tmp := false;
  end if;
  return tmp;
end;

constant APM_Q_C : integer := 27;

constant APM_FEXT_U : integer := 27;

constant APM_FEXT_D : integer := 24;

constant APM_XEXT_U : integer := 15;

constant APM_XEXT_D : integer := 8;

constant APM_SEXT_U : integer := 23;

constant APM_SEXT_D : integer := 16;

procedure apm_setspsr(
  mode : in  std_logic_vector(4 downto 0);
  spsr : inout  apm_spsr;
  cpsr : in  apm_cpsr
);

-- check weather <mode> has a spsr
function apm_is_hasspsr (
  mode : std_logic_vector(4 downto 0)
) return boolean;

end armpmodel;

package body armpmodel is

-------------------------------------------------------------------------------
  
function apm_is_privmode (
  mode : std_logic_vector(4 downto 0)
) return boolean is
  variable tmp : boolean;
begin
  tmp := true;
  if mode = APM_USR then
    tmp := false;
  end if;
  return tmp;
end;

-------------------------------------------------------------------------------

constant APM_N_C : integer := 31;
constant APM_Z_C : integer := 30;
constant APM_C_C : integer := 29;
constant APM_V_C : integer := 28;
constant APM_Q_C : integer := 27;

constant APM_I_C : integer := 7;
constant APM_F_C : integer := 6;
constant APM_T_C : integer := 5;
constant APM_MODE_U : integer := 4;
constant APM_MODE_D : integer := 0;

-- extensions
-- constant APM_FEXT_U : integer := 27;
-- constant APM_FEXT_D : integer := 24;
-- constant APM_XEXT_U : integer := 15;
-- constant APM_XEXT_D : integer := 8;
-- constant APM_SEXT_U : integer := 23;
-- constant APM_SEXT_D : integer := 16;

function apm_stdtocpsr (
  data : std_logic_vector
) return apm_cpsr is
  variable tmp : apm_cpsr;
begin
  
  tmp.ex.n := data(APM_N_C);
  tmp.ex.z := data(APM_Z_C);
  tmp.ex.c := data(APM_C_C);
  tmp.ex.v := data(APM_V_C);

  tmp.wr.i := data(APM_I_C);
  tmp.wr.f := data(APM_F_C);
  tmp.wr.t := data(APM_T_C);
  tmp.wr.mode := data(APM_MODE_U downto APM_MODE_D);

  -- extensions
  -- tmp.fext := data(ACP_FEXT_U downto ACP_FEXT_D);
  -- tmp.xext := data(ACP_XEXT_U downto ACP_XEXT_D);
  -- tmp.sext := data(ACP_SEXT_U downto ACP_SEXT_D);
  
  return tmp;
end;

function apm_cpsrtostd (
  cpsr : apm_cpsr
) return std_logic_vector is
  variable tmp : std_logic_vector(31 downto 0);
begin
  tmp := (others => '0');
  
  tmp(APM_N_C) := cpsr.ex.n;
  tmp(APM_Z_C) := cpsr.ex.z;
  tmp(APM_C_C) := cpsr.ex.c;
  tmp(APM_V_C) := cpsr.ex.v;
  tmp(APM_Q_C) := '0';

  tmp(APM_I_C) := cpsr.wr.i;
  tmp(APM_F_C) := cpsr.wr.f;
  tmp(APM_T_C) := cpsr.wr.t;
  
  tmp(APM_MODE_U downto APM_MODE_D) := cpsr.wr.mode;        

  -- extensions
  -- tmp(ACP_FEXT_U downto ACP_FEXT_D) := cpsr.fext;
  -- tmp(ACP_XEXT_U downto ACP_XEXT_D) := cpsr.xext;
  -- tmp(ACP_SEXT_U downto ACP_SEXT_D) := cpsr.sext;
  
  return tmp;
end;

function apm_msr (
  insn : std_logic_vector(31 downto 0);
  newcpsr : apm_cpsr;
  oldcpsr : apm_cpsr
) return apm_cpsr is
  variable tmp : apm_cpsr;
begin
  tmp := oldcpsr;

  -- +---+---+---+---+---+------------+---+---+---+------+
  -- | n | z | c | v | q |   dnm(raz) | i | f | t | mode |
  -- +---+---+---+---+---+------------+---+---+---+------+

  -- $(del)
  -- if opcode[25] == 1
  --   operand = 8_bit_immediate Rotate_Right (rotate_imm * 2)
  -- else /* opcode[25] == 0 */
  --   operand = Rm
  --
  -- if R == 0 then
  --   if field_mask[0] == 1 and InAPrivilegedMode() then
  --   CPSR[7:0] = operand[7:0]
  --   if field_mask[1] == 1 and InAPrivilegedMode() then
  --   CPSR[15:8] = operand[15:8]
  --   if field_mask[2] == 1 and InAPrivilegedMode() then
  --   CPSR[23:16] = operand[23:16]
  --   if field_mask[3] == 1 then
  --   CPSR[31:24] = operand[31:24]
  -- else /* R == 1 */
  --   if field_mask[0] == 1 and CurrentModeHasSPSR() then
  --   SPSR[7:0] = operand[7:0]
  --   if field_mask[1] == 1 and CurrentModeHasSPSR() then
  --   SPSR[15:8] = operand[15:8]
  --   if field_mask[2] == 1 and CurrentModeHasSPSR() then
  --   SPSR[23:16] = operand[23:16]
  --   if field_mask[3] == 1 and CurrentModeHasSPSR() then
  --   SPSR[31:24] = operand[31:24]
  -- $(/del)

  
  if insn(APM_MSR_C) = '1' then
    tmp.wr.i := newcpsr.wr.i;
    tmp.wr.f := newcpsr.wr.f;
    tmp.wr.t := newcpsr.wr.t;
    tmp.wr.mode := newcpsr.wr.mode;
  end if;
  if insn(APM_MSR_X) = '1' then
    -- extensions
    -- tmp.xext := newcpsr.xext;
  end if;
  if insn(APM_MSR_S) = '1' then
    -- extensions
    -- tmp.sext := newcpsr.sext;
  end if;
  if insn(APM_MSR_F) = '1' then
    tmp.ex.n := newcpsr.ex.n;
    tmp.ex.z := newcpsr.ex.z;
    tmp.ex.c := newcpsr.ex.c;
    tmp.ex.v := newcpsr.ex.v;
    -- extensions
    -- tmp.ex.fext := newcpsr.fext;
  end if;
  
  return tmp;
end;

-------------------------------------------------------------------------------

-- banked register mapping:
-- 
--          USR     SYS     SVC     ABT     UND     IRQ     FIQ  
--       +-------+-------+-------+-------+-------+-------+-------+
--R0-R7  |      
--       +-------+---------------------------------------+-------+
--R8-R12 |                                                R16-R20
--       +-------+---------------------------------------+-------+
--R13    |                   R24    R26     R28    R30      R21 
--       +-------+---------------------------------------+-------+
--R14    |                   R25    R27     R29    R31      R22
--       +-------+---------------------------------------+-------+

function apm_bankreg(
  mode : in std_logic_vector(4 downto 0);
  addr : in std_logic_vector
) return std_logic_vector is
variable tmp  : std_logic_vector(addr'high+1 downto 0);  -- +1: return is 5bits
variable bank : std_logic_vector(addr'high+1 downto 0);  
begin
  tmp := "0"&addr(addr'high downto 0);
  bank := "0"&addr(addr'high downto 0);
  case mode is
    when APM_USR => 
    when APM_SYS => 
    when APM_SVC =>
      bank := "1100" & not addr(0);
    when APM_ABT => 
      bank := "1101" & not addr(0);
    when APM_UND => 
      bank := "1110" & not addr(0);
    when APM_FIQ => 
      if addr(3) = '1' then
        bank(4 downto 3) := "10";
        tmp(4 downto 3) := "10";
      end if;
    when APM_IRQ => 
      bank := "1111" & not addr(0);
    when others => 
  end case;
  case addr(3 downto 0) is
    when "1101"|"1110" => tmp := bank;
    when others => 
  end case;
  return tmp;
end;

procedure apm_setspsr(
  mode : in  std_logic_vector(4 downto 0);
  spsr : inout  apm_spsr;
  cpsr : in  apm_cpsr
) is
begin
  case mode is
    when APM_SVC =>
      spsr.svc_SPSR := cpsr;
    when APM_ABT => 
      spsr.abt_SPSR := cpsr;
    when APM_UND => 
      spsr.und_SPSR := cpsr;
    when APM_IRQ => 
      spsr.irq_SPSR := cpsr;
    when APM_FIQ => 
      spsr.fiq_SPSR := cpsr;
    when others => 
  end case;
end;