/tmp/build_html/vhdl/arm/armiu_mestg.vhd : l8arm - synthesizable ARM v4 vhdl model.

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-- $(lic)
-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use work.armpctrl.all;
use work.armdecode.all;
use work.arm_comp.all;
use work.armpmodel.all;
use work.ctrl_comp.all;

entity armiu_mestg is
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_mestg_typ_in;
    o       : out armiu_mestg_typ_out
    );
end armiu_mestg;

architecture rtl of armiu_mestg is

  type armiu_mestg_tmp_type is record
    o       : armiu_mestg_typ_out;
    commit : std_logic;
    meid : std_logic_vector(2 downto 0);
    wrid : std_logic_vector(2 downto 0);
  end record;
  type armiu_mestg_reg_type is record
    pctrl : apc_pctrl;
    mexc : std_logic;
  end record;
  type armiu_mestg_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_mestg_tmp_type;
     -- pragma translate_on
  end record;
  signal r, c       : armiu_mestg_reg_type;
  signal rdbg, cdbg : armiu_mestg_dbg_type;

begin  
    
  p0: process (clk, rst, r, i  )
    variable v    : armiu_mestg_reg_type;
    variable t    : armiu_mestg_tmp_type;
    variable vdbg : armiu_mestg_dbg_type;
  begin 
    
    -- $(init(t:armiu_mestg_tmp_type))
    
    v := r;
    t.commit := not i.flush_v ;

    t.meid := i.pstate.fromME_pctrl_r.insn.id;
    t.wrid := i.pstate.fromWR_pctrl_r.insn.id;
    
    --if i.dco.me_mexc = '1' then
    --  v.mexc := '1';
    --end if;
    
    -- swp addresses
    t.o.dci.addr_in := i.pstate.fromDM_pctrl_r.data1;
    case i.pstate.fromDM_pctrl_r.insn.decinsn is
      when type_arm_swp =>
        t.o.dci.addr_in(1 downto 0) := (others => '0');
      when others =>
    end case;
    t.o.dci.addr_re := r.pctrl.data1;
    t.o.dci.atomic_readwrite := '0';
    case r.pctrl.insn.decinsn is
      when type_arm_swp =>
        t.o.dci.addr_re(1 downto 0) := (others => '0');
        t.o.dci.atomic_readwrite := '1';
      when others =>
    end case;
    
    -- reset
    if ( rst = '0' ) then
      v.mexc := '0';
    end if;
    
    -- pipeline propagation
    t.o.pctrl_r := r.pctrl;
    t.o.toWR_pctrl_v := v.pctrl;
    
    -- irq
    if (not (i.irqo.irl = IRQ_NOIRQ)) and
       (not (t.meid = t.wrid)) then
      t.commit := '0';
      t.o.toWR_pctrl_v.wr.wrop_trap.trap := '1';
      t.o.toWR_pctrl_v.wr.wrop_trap.traptype := apm_trap_irq;
      t.o.toWR_pctrl_v.data2(3 downto 0) := i.irqo.irl;
    end if;
    
    -- dcache input
    t.o.dci.data_in  := i.pstate.fromDM_pctrl_r.data2;
    t.o.dci.data_re  := r.pctrl.data2;
    
    t.o.dci.addrin_re := r.pctrl.me.meop_param.addrin and
                         r.pctrl.valid; 
    t.o.dci.annul := (not t.commit) ; 
    t.o.dci.forcewrite := '0';
    t.o.dci.forceread := '0';
    
    t.o.dci.param_r.size      := r.pctrl.me.meop_param.size;
    t.o.dci.param_r.read      := r.pctrl.me.meop_param.read;
    t.o.dci.param_r.lock      := r.pctrl.me.meop_param.lock;
    t.o.dci.param_r.writedata := r.pctrl.me.meop_param.writedata;
    t.o.dci.param_r.addrin    := r.pctrl.me.meop_param.addrin;
    t.o.dci.param_r.signed    := r.pctrl.me.meop_param.signed;
    
    -- pipeline flush
    if not (t.commit = '1') then
      t.o.toWR_pctrl_v.valid := '0';
    end if;
    
    if i.pstate.hold_r.hold = '0' then
      v.pctrl := i.fromDM_pctrl_v;
    end if;
    
    c <= v;
    
    o <= t.o;
    
    -- pragma translate_off
    vdbg := rdbg;
    vdbg.dbg := t;
    cdbg <= vdbg;
    -- pragma translate_on  
    
  end process p0;
    
  pregs : process (clk, c)
  begin
    if rising_edge(clk) then
      r <= c;
      -- pragma translate_off
      rdbg <= cdbg;
      -- pragma translate_on
    end if;
  end process;
  
end rtl;

File /tmp/build_html/vhdl/core/ctrl/ctrl_comp.vhd
used by /tmp/build_html/vhdl/core/ctrl/irqctrl.vhd
used by /tmp/build_html/vhdl/core/ctrl/irqctrl2.vhd
used by /tmp/build_html/vhdl/core/ctrl/timers.vhd
used by /tmp/build_html/vhdl/arm/arm_comp.vhd
used by /tmp/build_html/vhdl/arm/armiu_mestg.vhd
used by /tmp/build_html/vhdl/core/soc_gen.vhd
used by /tmp/build_html/vhdl/core/core.vhd

File /tmp/build_html/vhdl/arm/armiu_mestg.vhd

Enum astates defined in /tmp/build_html/vhdl/sparc/mmu_acache.vhd

type astates is (idle, dcache, icache, mmu);

Enum rdatatype defined in /tmp/build_html/vhdl/sparc/mmu_icache.vhd

type rdatatype is (itag, idata, memory);

Type cli_hold defined in /tmp/build_html/vhdl/core/libs/corelib.vhd

type cli_hold is record
   hold : std_logic; -- hold
   dhold : std_logic; -- dcache hold
   ihold : std_logic; -- icache hold
end record;

Enum mcycletype defined in /tmp/build_html/vhdl/peripherals/mem/sdmctrl.vhd

type mcycletype is (midle, active, leadout);

Constant zero defined in /tmp/build_html/vhdl/sparc/pci_gr.vhd

constant zero : std_logic_vector(31 downto 0) := (others =>

Type apm_excpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_excpsr is record
   n      : std_logic;                  -- negative
   z      : std_logic;                  -- zero
   c      : std_logic;                  -- carry
   v      : std_logic;                  -- overflow
   -- extensions
   -- fext   : std_logic_vector(3 downto 0);  -- cpsr(27:24)
   -- xext   : std_logic_vector(7 downto 0);  -- cpsr(15:8)
   -- sext   : std_logic_vector(7 downto 0);  -- cpsr(23:16)
end record;

Type apm_wrcpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_wrcpsr is record
   i      : std_logic;                  -- [7] irq
   f      : std_logic;                  -- [6] fiq
   t      : std_logic;                  -- [5] thumb
   mode   : std_logic_vector(4 downto 0);
-- pragma translate_off
--   dbgmode  : aba_atyp_dbgpmode;       -- readable pmode for dbg
-- pragma translate_on
end record;

Type apm_cpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_cpsr is record
   ex : apm_excpsr;
   wr : apm_wrcpsr;
end record;

Enum ade_insntyp defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_insntyp is (
  ade_typmem,
  ade_typalu,
  ade_typmisc,
  ade_typcp
);

Enum ade_decinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_decinsn is (
  type_arm_invalid,type_arm_nop,    type_arm_mrs,    type_arm_bx,    type_arm_mul,   type_arm_mla,
  type_arm_swp,    type_arm_sumull, type_arm_sumlal, type_arm_strhb, type_arm_ldrhb, type_arm_and,
  type_arm_sub,    type_arm_eor,    type_arm_rsb,    type_arm_add,   type_arm_sbc,   type_arm_adc, 
  type_arm_msr,    type_arm_teq,    type_arm_cmn,    type_arm_tst,   type_arm_cmp,   type_arm_orr, 
  type_arm_mov,    type_arm_mvn,    type_arm_str1,   type_arm_str2,  type_arm_str3,  type_arm_ldr1,
  type_arm_stm,    type_arm_ldm,    type_arm_b,      type_arm_swi,   type_arm_cdp,   type_arm_mrc,
  type_arm_mcr,    type_arm_stc,    type_arm_ldc,    type_arm_rsc,   type_arm_bic,   type_arm_undefined
);

Enum ade_DAPRAM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_DAPRAM is (
  ade_DAPRAM_simm,       -- OP2 shieft with imm 
  ade_DAPRAM_sreg,       -- OP2 shieft with reg 
  ade_DAPRAM_immrot      -- OP2 immidiate rotated
);

Enum ade_LDSTAMxLSV4AM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_LDSTAMxLSV4AM is (
  ade_LDSTAMxLSV4AM_imm,  -- addr v1 imm
                          -- addr v4 imm
  ade_LDSTAMxLSV4AM_reg   -- addr v1 reg (shieft with imm)
                          -- addr v4 reg
);

Enum icycletype defined in /tmp/build_html/vhdl/peripherals/mem/sdmctrl.vhd

type icycletype is (iidle, pre, ref1, ref2, lmode, finish);

Enum ade_pos defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_pos is (
  ade_pre,      -- pre indexed
  ade_post      -- post indexed
);

Enum ash_sdir defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd

type ash_sdir is (
  ash_sdir_snone,    -- no shieft
  ash_sdir_slsl,     -- LSL #: logical shieft left 
  ash_sdir_slsr,     -- LSR #: logical shieft righ
  ash_sdir_sasr,     -- ASR #: arithmetic shieft left
  ash_sdir_sror,     -- ROR #: rotate 
  ash_sdir_srrx      -- RRX #: rotate 1 with carry
);

Type ade_amode defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_amode is record
  DAPRAM_typ           : ade_DAPRAM;
  LDSTAM_typ           : ade_LDSTAMxLSV4AM;
  LSV4AM_typ           : ade_LDSTAMxLSV4AM;
  LDSTAMxLSV4AM_pos    : ade_pos;
  DAPRAMxLDSTAM_sdir   : ash_sdir;
  LDSTAMxLSV4AM_uacc   : std_logic;
  LDSTAMxLSV4AM_wb     : std_logic;
end record;

Type ade_insn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_insn is record
  pc_8    : std_logic_vector(31 downto 0);
  insn    : std_logic_vector(31 downto 0);
  insntyp : ade_insntyp;
  decinsn : ade_decinsn;
  am      : ade_amode;
  valid   : std_logic;
  id      : std_logic_vector(2 downto 0);
end record;

Type apc_rrstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rrstg is record
  -- operations
  dummy : std_logic;
end record;

Enum apc_rsop_opsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsop_opsrc is (
  apc_opsrc_through,
  apc_opsrc_buf,
  apc_opsrc_alures,
  apc_opsrc_none
);

Enum apc_rsop_bufsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsop_bufsrc is (
  apc_bufsrc_none,
  apc_bufsrc_through,
  apc_bufsrc_alures
);

Enum ash_styp defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd

type ash_styp is (
  ash_styp_none,  -- no shieft
  ash_styp_immrot,-- DAPRAM: OP2 immidiate rotated
  ash_styp_simm,  -- DAPRAM: OP2 shieft with imm, LDSTAM: addr v1 reg (adm_LDSTAM_reg) 
  ash_styp_sreg   -- DAPRAM: OP2 shieft with reg  
);

Enum txfsmtype defined in /tmp/build_html/vhdl/sparc/dcom_uart.vhd

type txfsmtype is (idle, data, stopbit);

Type apc_rsstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsstg is record
  -- operations
  rsop_op1_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_op2_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source
  rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source
  rsop_styp     : ash_styp;        -- RSSTG shieft op
  rsop_sdir     : ash_sdir;        -- RSSTG shieft dir
  -- data
  rs_shieftcarryout : std_logic;   -- RSSTG shiefter carry out
end record;

Enum apc_exop_datasrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exop_datasrc is (
  apc_datasrc_aluout,
  apc_datasrc_buf,
  apc_datasrc_none
);

Enum apc_exop_bufsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exop_bufsrc is (
  apc_exbufsrc_none,
  apc_exbufsrc_aluout,
  apc_exbufsrc_op1
);

Enum cpins_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type cpins_type is (none, cpop, load, store);

Type apc_exstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exstg is record
  -- operations
  exop_aluop    : std_logic_vector(3 downto 0);  -- EXSTG alu operation
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source
  exop_setcpsr  : std_logic;         -- EXSTG set cpsr
  -- data                                   
  ex_cpsr : apm_cpsr;           -- EXSTG store old cpsr
end record;

Type apc_dmstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_dmstg is record
  dummy : std_logic;
end record;

Enum lmd_memsize defined in /tmp/build_html/vhdl/libs/memdef.vhd

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

Type gdcl_param defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

Type apc_mestg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_mestg is record
  -- operation
  meop_enable : std_logic;
  meop_param  : gdcl_param;
  -- data
  mexc   : std_logic;
end record;

Constant APM_RREAL_U defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

constant APM_RREAL_U : integer := 4;

Constant APM_RREAL_D defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

constant APM_RREAL_D : integer := 0;

Enum slavestate defined in /tmp/build_html/vhdl/sparc/ahbtest.vhd

type slavestate is (idle, error, split, retry, ws1);

Enum dsnoop_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

type dsnoop_type is (none, slow, fast);

Enum apm_trap defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_trap is (
  apm_trap_reset,   -- reset
  apm_trap_undef,   -- undefined (EXSTG)
  apm_trap_swi,     -- software interrupt (DRSTG)
  apm_trap_prefch,  -- prefetch error (IMSTG)
  apm_trap_dabort,  -- data abort error (MESTG)
  apm_trap_irq,     -- interrupt
  apm_trap_fiq      -- fast interrupt
);

Type apm_trapctrl defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_trapctrl is record
  traptype : apm_trap;
  trap     : std_logic;
end record;

Type apc_wrstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_wrstg is record
  -- operation
  wrop_rd      : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  wrop_rdvalid : std_logic;
  wrop_setspsr : std_logic;
  wrop_trap    : apm_trapctrl;
end record;

Type apc_pctrl defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_pctrl is record
  insn : ade_insn;
  valid : std_logic;
  rr : apc_rrstg;
  rs : apc_rsstg;
  ex : apc_exstg;
  dm : apc_dmstg;
  me : apc_mestg;
  wr : apc_wrstg;
  data1 : std_logic_vector(31 downto 0);
  data2 : std_logic_vector(31 downto 0);
end record;

Type apc_pstate defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_pstate is record
  hold_r    : cli_hold;
  nextinsn_v : std_logic;
  dabort_v : std_logic;
  -- active cpsr
  fromEX_cpsr_r : apm_cpsr;
  -- pctrls of all stages from rrstg on 
  fromRR_pctrl_r : apc_pctrl;
  fromRS_pctrl_r : apc_pctrl;
  fromEX_pctrl_r : apc_pctrl;
  fromDM_pctrl_r : apc_pctrl;
  fromME_pctrl_r : apc_pctrl;
  fromWR_pctrl_r : apc_pctrl;
end record;

Type irq_iu_out_type defined in /tmp/build_html/vhdl/core/ctrl/ctrl_comp.vhd

type irq_iu_out_type is record
  irl   	: std_logic_vector(3 downto 0);   -- zero = no irq
end record;

Type armiu_mestg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_mestg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   irqo : irq_iu_out_type;
   fromDM_pctrl_v : apc_pctrl;
end record;

Type gendc_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gendc_type_in is record
  addr_in : std_logic_vector(31 downto 0);  -- incoming
  data_in : std_logic_vector(31 downto 0);
  addr_re : std_logic_vector(31 downto 0);  -- registered
  data_re : std_logic_vector(31 downto 0);
  addrin_re : std_logic;

  -- todo: locking on atomic load store does not work yet
  -- until no multiprocessor system is implemented it's defered to the future

  atomic_readwrite : std_logic;
  
  forcewrite : std_logic;
  forceread : std_logic;
  
  param_r : gdcl_param;
  annul : std_logic;
end record;

Type armiu_mestg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_mestg_typ_out is record
   pctrl_r : apc_pctrl;
   toWR_pctrl_v : apc_pctrl;
   dci   : gendc_type_in;
end record;

Type armiu_mestg_tmp_type defined in /tmp/build_html/vhdl/arm/armiu_mestg.vhd

type armiu_mestg_tmp_type is record
    o       : armiu_mestg_typ_out;
    commit : std_logic;
    meid : std_logic_vector(2 downto 0);
    wrid : std_logic_vector(2 downto 0);
  end record;

Type armiu_mestg_reg_type defined in /tmp/build_html/vhdl/arm/armiu_mestg.vhd

type armiu_mestg_reg_type is record
    pctrl : apc_pctrl;
    mexc : std_logic;
  end record;

Type armiu_mestg_dbg_type defined in /tmp/build_html/vhdl/arm/armiu_mestg.vhd

type armiu_mestg_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_mestg_tmp_type;
     -- pragma translate_on
  end record;

Constant IRQ_NOIRQ defined in /tmp/build_html/vhdl/core/ctrl/ctrl_comp.vhd

constant IRQ_NOIRQ :std_logic_vector(3 downto 0) := (others =>

Enum states defined in /tmp/build_html/vhdl/sparc/mmutw.vhd

type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution