type astates is (idle, dcache, icache, mmu);

type rdatatype is (itag, idata, memory);

type cli_hold is record
   hold : std_logic; -- hold
   dhold : std_logic; -- dcache hold
   ihold : std_logic; -- icache hold
end record;

type mcycletype is (midle, active, leadout);

constant zero : std_logic_vector(31 downto 0) := (others =>

type apm_excpsr is record
   n      : std_logic;                  -- negative
   z      : std_logic;                  -- zero
   c      : std_logic;                  -- carry
   v      : std_logic;                  -- overflow
   -- extensions
   -- fext   : std_logic_vector(3 downto 0);  -- cpsr(27:24)
   -- xext   : std_logic_vector(7 downto 0);  -- cpsr(15:8)
   -- sext   : std_logic_vector(7 downto 0);  -- cpsr(23:16)
end record;

type apm_wrcpsr is record
   i      : std_logic;                  -- [7] irq
   f      : std_logic;                  -- [6] fiq
   t      : std_logic;                  -- [5] thumb
   mode   : std_logic_vector(4 downto 0);
-- pragma translate_off
--   dbgmode  : aba_atyp_dbgpmode;       -- readable pmode for dbg
-- pragma translate_on
end record;

type apm_cpsr is record
   ex : apm_excpsr;
   wr : apm_wrcpsr;
end record;

type ade_insntyp is (
  ade_typmem,
  ade_typalu,
  ade_typmisc,
  ade_typcp
);

type ade_decinsn is (
  type_arm_invalid,type_arm_nop,    type_arm_mrs,    type_arm_bx,    type_arm_mul,   type_arm_mla,
  type_arm_swp,    type_arm_sumull, type_arm_sumlal, type_arm_strhb, type_arm_ldrhb, type_arm_and,
  type_arm_sub,    type_arm_eor,    type_arm_rsb,    type_arm_add,   type_arm_sbc,   type_arm_adc, 
  type_arm_msr,    type_arm_teq,    type_arm_cmn,    type_arm_tst,   type_arm_cmp,   type_arm_orr, 
  type_arm_mov,    type_arm_mvn,    type_arm_str1,   type_arm_str2,  type_arm_str3,  type_arm_ldr1,
  type_arm_stm,    type_arm_ldm,    type_arm_b,      type_arm_swi,   type_arm_cdp,   type_arm_mrc,
  type_arm_mcr,    type_arm_stc,    type_arm_ldc,    type_arm_rsc,   type_arm_bic,   type_arm_undefined
);

type ade_DAPRAM is (
  ade_DAPRAM_simm,       -- OP2 shieft with imm 
  ade_DAPRAM_sreg,       -- OP2 shieft with reg 
  ade_DAPRAM_immrot      -- OP2 immidiate rotated
);

type ade_LDSTAMxLSV4AM is (
  ade_LDSTAMxLSV4AM_imm,  -- addr v1 imm
                          -- addr v4 imm
  ade_LDSTAMxLSV4AM_reg   -- addr v1 reg (shieft with imm)
                          -- addr v4 reg
);

type icycletype is (iidle, pre, ref1, ref2, lmode, finish);

type ade_pos is (
  ade_pre,      -- pre indexed
  ade_post      -- post indexed
);

type ash_sdir is (
  ash_sdir_snone,    -- no shieft
  ash_sdir_slsl,     -- LSL #: logical shieft left 
  ash_sdir_slsr,     -- LSR #: logical shieft righ
  ash_sdir_sasr,     -- ASR #: arithmetic shieft left
  ash_sdir_sror,     -- ROR #: rotate 
  ash_sdir_srrx      -- RRX #: rotate 1 with carry
);

type ade_amode is record
  DAPRAM_typ           : ade_DAPRAM;
  LDSTAM_typ           : ade_LDSTAMxLSV4AM;
  LSV4AM_typ           : ade_LDSTAMxLSV4AM;
  LDSTAMxLSV4AM_pos    : ade_pos;
  DAPRAMxLDSTAM_sdir   : ash_sdir;
  LDSTAMxLSV4AM_uacc   : std_logic;
  LDSTAMxLSV4AM_wb     : std_logic;
end record;

type ade_insn is record
  pc_8    : std_logic_vector(31 downto 0);
  insn    : std_logic_vector(31 downto 0);
  insntyp : ade_insntyp;
  decinsn : ade_decinsn;
  am      : ade_amode;
  valid   : std_logic;
  id      : std_logic_vector(2 downto 0);
end record;

type apc_rrstg is record
  -- operations
  dummy : std_logic;
end record;

type apc_rsop_opsrc is (
  apc_opsrc_through,
  apc_opsrc_buf,
  apc_opsrc_alures,
  apc_opsrc_none
);

type apc_rsop_bufsrc is (
  apc_bufsrc_none,
  apc_bufsrc_through,
  apc_bufsrc_alures
);

type ash_styp is (
  ash_styp_none,  -- no shieft
  ash_styp_immrot,-- DAPRAM: OP2 immidiate rotated
  ash_styp_simm,  -- DAPRAM: OP2 shieft with imm, LDSTAM: addr v1 reg (adm_LDSTAM_reg) 
  ash_styp_sreg   -- DAPRAM: OP2 shieft with reg  
);

type txfsmtype is (idle, data, stopbit);

type apc_rsstg is record
  -- operations
  rsop_op1_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_op2_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source
  rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source
  rsop_styp     : ash_styp;        -- RSSTG shieft op
  rsop_sdir     : ash_sdir;        -- RSSTG shieft dir
  -- data
  rs_shieftcarryout : std_logic;   -- RSSTG shiefter carry out
end record;

type apc_exop_datasrc is (
  apc_datasrc_aluout,
  apc_datasrc_buf,
  apc_datasrc_none
);

type apc_exop_bufsrc is (
  apc_exbufsrc_none,
  apc_exbufsrc_aluout,
  apc_exbufsrc_op1
);

type cpins_type is (none, cpop, load, store);

type apc_exstg is record
  -- operations
  exop_aluop    : std_logic_vector(3 downto 0);  -- EXSTG alu operation
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source
  exop_setcpsr  : std_logic;         -- EXSTG set cpsr
  -- data                                   
  ex_cpsr : apm_cpsr;           -- EXSTG store old cpsr
end record;

type apc_dmstg is record
  dummy : std_logic;
end record;

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

type apc_mestg is record
  -- operation
  meop_enable : std_logic;
  meop_param  : gdcl_param;
  -- data
  mexc   : std_logic;
end record;

constant APM_RREAL_U : integer := 4;

constant APM_RREAL_D : integer := 0;

type slavestate is (idle, error, split, retry, ws1);

type dsnoop_type is (none, slow, fast);

type apm_trap is (
  apm_trap_reset,   -- reset
  apm_trap_undef,   -- undefined (EXSTG)
  apm_trap_swi,     -- software interrupt (DRSTG)
  apm_trap_prefch,  -- prefetch error (IMSTG)
  apm_trap_dabort,  -- data abort error (MESTG)
  apm_trap_irq,     -- interrupt
  apm_trap_fiq      -- fast interrupt
);

type apm_trapctrl is record
  traptype : apm_trap;
  trap     : std_logic;
end record;

type apc_wrstg is record
  -- operation
  wrop_rd      : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  wrop_rdvalid : std_logic;
  wrop_setspsr : std_logic;
  wrop_trap    : apm_trapctrl;
end record;

type apc_pctrl is record
  insn : ade_insn;
  valid : std_logic;
  rr : apc_rrstg;
  rs : apc_rsstg;
  ex : apc_exstg;
  dm : apc_dmstg;
  me : apc_mestg;
  wr : apc_wrstg;
  data1 : std_logic_vector(31 downto 0);
  data2 : std_logic_vector(31 downto 0);
end record;

type apc_pstate is record
  hold_r    : cli_hold;
  nextinsn_v : std_logic;
  dabort_v : std_logic;
  -- active cpsr
  fromEX_cpsr_r : apm_cpsr;
  -- pctrls of all stages from rrstg on 
  fromRR_pctrl_r : apc_pctrl;
  fromRS_pctrl_r : apc_pctrl;
  fromEX_pctrl_r : apc_pctrl;
  fromDM_pctrl_r : apc_pctrl;
  fromME_pctrl_r : apc_pctrl;
  fromWR_pctrl_r : apc_pctrl;
end record;

type ade_deinsn is record
  insn   : ade_insn;
  trap   : std_logic;
end record;

type armiu_drstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromDE_insn_r : ade_deinsn;
   fromDE_insn_v : ade_deinsn;
   fromRR_nextmicro_v : std_logic;
   fromWR_dabort_v : std_logic;

   fromCPDE_accept : std_logic;
   fromCPDE_busy : std_logic;
   fromCPDE_last : std_logic;

end record;

type apc_micro is record
  pctrl : apc_pctrl;
  valid : std_logic;
  r1, r2 : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  r1_valid, r2_valid : std_logic;
end record;

type armiu_drstg_typ_out is record
   nextinsn_v : std_logic;
   toRR_micro_v : apc_micro;
   id : std_logic_vector(2 downto 0);
end record;

constant ACM_CNT_SZ    : integer := 5;

type acm_ctrlout is record
  nextinsn : std_logic;
  nextcnt  : std_logic;
  hold     : std_logic;     
end record;

type acm_ctrlin is record
  cnt   : std_logic_vector(ACM_CNT_SZ-1 downto 0);
  insn  : ade_insn;
  ctrlo : acm_ctrlout;                  -- preinitialized ctrlo
end record;

type armcmd_al_typ_in is record
                           
   ctrli    : acm_ctrlin;
   
end record;

type armcmd_sr_typ_in is record
                           
   ctrli    : acm_ctrlin;

   deid  : std_logic_vector(2 downto 0);  -- (destg.pctrl.id)

   exid  : std_logic_vector(2 downto 0);  -- (exstg.pctrl.id)
   exvalid : std_logic;                   -- (exstg.pctrl.valid)

   wrid  : std_logic_vector(2 downto 0);  -- (wrstg.pctrl.id) 
   wrvalid : std_logic;                   -- (wrstg.pctrl.valid)

end record;

type acm_regsrc is (
  acm_none,
  acm_rrn,
  acm_rrm,
  acm_rrd,
  acm_rrs,
  acm_local
);

type acm_rdsrc is (
  acm_rdnone,
  acm_rdrrd,
  acm_rdrrn,
  acm_rdlocal,
  acm_rdpc,
  acm_rdlink
);

type acm_ctrlmemout is record
                       
  data1            : std_logic_vector(31 downto 0); -- immidiate 1 (pctrl.data1)
  data2            : std_logic_vector(31 downto 0); -- immidiate 2 (pctrl.data2)

  -- rrstg:
  r1_src    : acm_regsrc;  -- (micro.r1)
  r2_src    : acm_regsrc;  -- (micro.r2)
  rd_src    : acm_rdsrc;   -- (pctrl.wr.wrop_rd)
  
  -- rsstg: 
  rsop_op1_src     : apc_rsop_opsrc;    -- EXSTG operand1 source (pctrl.rs.rsop_op1_src)
  rsop_op2_src     : apc_rsop_opsrc;    -- EXSTG operand1 source (pctrl.rs.rsop_op2_src)
  rsop_buf1_src    : apc_rsop_bufsrc;   -- RSSTG buffer1 source (pctrl.rs.rsop_buf1_src)
  rsop_buf2_src    : apc_rsop_bufsrc;   -- RSSTG buffer2 source (pctrl.rs.rsop_buf2_src)
  
  -- exstg:
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source (pctrl.ex.data_src)
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source (pctl.ex.exop_buf_src)
  
  -- mestg:
  meop_param  : gdcl_param;  -- (pctl.me.meop_param)
  meop_enable : std_logic;   -- (pctl.me.meop_enable)
  
end record;

type armcmd_ld_typ_in is record
                           
   ctrli    : acm_ctrlin;

   ctrlmemo : acm_ctrlmemout;
      
end record;

type armcmd_st_typ_in is record
                           
   ctrli    : acm_ctrlin;

   ctrlmemo : acm_ctrlmemout;
            
end record;

constant APM_REGLIST_SZ : integer := 16;

type acm_ctrlmult_in is record
  ctrlmemo  : acm_ctrlmemout;
  ival  : std_logic_vector(31 downto 0);
  soff  : std_logic_vector(31 downto 0);
  eoff  : std_logic_vector(31 downto 0);
  reglist  : std_logic_vector(APM_REGLIST_SZ-1 downto 0);
  mem   : std_logic;                    -- mem still present in pipeline
  dabort   : std_logic;                    -- mem still present in pipeline
end record;

type armcmd_lm_typ_in is record
                           
   ctrli    : acm_ctrlin;

   ctrlmulti : acm_ctrlmult_in;
   
end record;

type armcmd_sm_typ_in is record
                           
   ctrli    : acm_ctrlin;

   ctrlmulti : acm_ctrlmult_in;
   
end record;

type armcmd_sw_typ_in is record
                           
   ctrli    : acm_ctrlin;
   
   ctrlmemo : acm_ctrlmemout;

end record;

type armcmd_cr_typ_in is record
                           
   ctrli    : acm_ctrlin;

   fromCP_busy : std_logic;

end record;

type armcmd_cl_typ_in is record
                           
   ctrli    : acm_ctrlin;
   
   ctrlmemo : acm_ctrlmemout;
   fromCP_busy : std_logic;
   fromCP_last : std_logic;

end record;

type armcmd_cs_typ_in is record
                           
   ctrli    : acm_ctrlin;
   
   ctrlmemo : acm_ctrlmemout;
   fromCP_busy : std_logic;
   fromCP_last : std_logic;

end record;

type armcmd_bl_typ_in is record
                           
   ctrli    : acm_ctrlin;


end record;

constant APM_REG_U : integer := 3;

constant APM_REG_D : integer := 0;

type armiu_drstg_tmp_type is record
    o       : armiu_drstg_typ_out;
    cmdali  : armcmd_al_typ_in;
    cmdsri  : armcmd_sr_typ_in;
    cmdldi  : armcmd_ld_typ_in;
    cmdsti  : armcmd_st_typ_in;
    cmdlmi  : armcmd_lm_typ_in;
    cmdsmi  : armcmd_sm_typ_in;
    cmdswi  : armcmd_sw_typ_in;
    cmdcri  : armcmd_cr_typ_in;
    cmdcli  : armcmd_cl_typ_in;
    cmdcsi  : armcmd_cs_typ_in;
    cmdbli  : armcmd_bl_typ_in;
    
    ctrli : acm_ctrlin;
    ctrlo : acm_ctrlout;
    pctrl, pctrl_bypass : apc_pctrl;
    
    commit : std_logic;
    insn : std_logic_vector(31 downto 0);
    trap   : apm_trapctrl;
    nextmicro, mem : std_logic;
    micro : apc_micro;
    am : ade_amode;
    
    r1_src, r2_src : acm_regsrc; 
    rd_src : acm_rdsrc;

    rn, rm, rd, rs, rlink, rpc : std_logic_vector(APM_REG_U downto APM_REG_D);
    nr : std_logic_vector(APM_REG_U downto APM_REG_D);
    nr_i : integer;
    nr_c : std_logic;
    startoff, endoff, incval : std_logic_vector(31 downto 0);
    m1, m2, md: std_logic_vector(APM_REG_U downto APM_REG_D);
    m1_valid, m2_valid: std_logic;
    rr1, rr2, rrd: std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
    rmode : std_logic_vector(4 downto 0);
    
  end record;

type armiu_drstg_reg_type is record
    cnt : std_logic_vector(ACM_CNT_SZ-1 downto 0);
    reglist : std_logic_vector(APM_REGLIST_SZ-1 downto 0);
  end record;

type adg_dbgpmode is (
  adg_usr,
  adg_sys,
  adg_svc,
  adg_abt,
  adg_und,
  adg_irq,
  adg_fiq,
  adg_invalid
);

type armiu_drstg_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_drstg_tmp_type;
     dbgpmode : adg_dbgpmode;
     dbgrmode : adg_dbgpmode;
     -- pragma translate_on
  end record;

type armcmd_al_typ_out is record
   
   ctrlo    : acm_ctrlout;

   -- rrstg
   r1_src    : acm_regsrc;           -- (micro.r1)
   r2_src    : acm_regsrc;           -- (micro.r2)
   rd_src    : acm_rdsrc;            -- (pctrl.wr.wrop_rd)
  
   -- rsstg:
   rsop_op1_src : apc_rsop_opsrc;    -- EXSTG operand1 source (pctrl.rs.rsop_op1_src)
   rsop_op2_src : apc_rsop_opsrc;    -- EXSTG operand2 source (pctrl.rs.rsop_op2_src)
   rsop_buf2_src : apc_rsop_bufsrc;  -- RSSTG buffer1 source (pctrl.rs.rsop_buf2_src)
  
   
end record;

type armcmd_sr_typ_out is record
                            
   ctrlo    : acm_ctrlout;

   -- rrstg:
   r2_src    : acm_regsrc;                 -- (micro.r2)
   rd_src    : acm_rdsrc;                  -- (pctrl.wr.wrop_rd)
  
   -- rsstg:
   rsop_styp        : ash_styp;            -- RSSTG shieft op (pctrl.rs.rsop_styp)
   rsop_sdir        : ash_sdir;            -- RSSTG shieft dir (pctrl.rs.rsop_sdir)
   rsop_op2_src     : apc_rsop_opsrc;      -- EXSTG operand2 source (pctrl.rs.rsop_op2_src)
  
   -- exstg:
   exop_setcpsr : std_logic;               -- EXSTG set cpsr (pctrl.ex.exop_setcpsr)
   
end record;

type armcmd_ld_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;
   
   rsop_styp        : ash_styp;  -- RSSTG shieft op (pctrl.rs.rsop_styp)
   rsop_sdir        : ash_sdir;  -- RSSTG shieft dir (pctrl.rs.rsop_sdir)

end record;

type armcmd_st_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;
   
   rsop_styp        : ash_styp;  -- RSSTG shieft op (pctrl.rs.rsop_styp)
   rsop_sdir        : ash_sdir;  -- RSSTG shieft dir (pctrl.rs.rsop_sdir)

end record;

type armcmd_lm_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;

end record;

type armcmd_sm_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;

end record;

type armcmd_sw_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;

end record;

type armcmd_cr_typ_out is record
   
   ctrlo    : acm_ctrlout;

   r1_src    : acm_regsrc;           -- (micro.r1)
   rd_src    : acm_rdsrc;            -- (pctrl.wr.wrop_rd)

end record;

type armcmd_cs_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;

end record;

type armcmd_cl_typ_out is record
   
   ctrlo    : acm_ctrlout;

   ctrlmemo : acm_ctrlmemout;

end record;

type armcmd_bl_typ_out is record
                            
   ctrlo    : acm_ctrlout;

   r1_src    : acm_regsrc;  -- (micro.r1)
   r2_src    : acm_regsrc;  -- (micro.r2)
   rd_src    : acm_rdsrc;   -- (pctrl.wr.wrop_rd)
  
   rsop_op2_src     : apc_rsop_opsrc;    -- EXSTG operand1 source (pctrl.rs.rsop_op2_src)
  
   data2            : std_logic_vector(31 downto 0); -- immidiate 1 (pctlr.data2)
   
end record;

constant APM_REG_LINK   : std_logic_vector(3 downto 0) := "1110";

function priority(v : std_logic_vector(31 downto 0)) return std_logic_vector is
begin
  if    v(31) = '1' then return("11111");
  elsif v(30) = '1' then return("11110");
  elsif v(29) = '1' then return("11101");
  elsif v(28) = '1' then return("11100");
  elsif v(27) = '1' then return("11011");
  elsif v(26) = '1' then return("11010");
  elsif v(25) = '1' then return("11001");
  elsif v(24) = '1' then return("11000");
  elsif v(23) = '1' then return("10111");
  elsif v(22) = '1' then return("10110");
  elsif v(21) = '1' then return("10101");
  elsif v(20) = '1' then return("10100");
  elsif v(19) = '1' then return("10011");
  elsif v(18) = '1' then return("10010");
  elsif v(17) = '1' then return("10001");
  elsif v(16) = '1' then return("10000");
  elsif v(15) = '1' then return("01111");
  elsif v(14) = '1' then return("01110");
  elsif v(13) = '1' then return("01101");
  elsif v(12) = '1' then return("01100");
  elsif v(11) = '1' then return("01011");
  elsif v(10) = '1' then return("01010");
  elsif v( 9) = '1' then return("01001");
  elsif v( 8) = '1' then return("01000");
  elsif v( 7) = '1' then return("00111");
  elsif v( 6) = '1' then return("00110");
  elsif v( 5) = '1' then return("00101");
  elsif v( 4) = '1' then return("00100");
  elsif v( 3) = '1' then return("00011");
  elsif v( 2) = '1' then return("00010");
  elsif v( 1) = '1' then return("00001");
  else return ("00000"); end if;
end;

function als_getnextpos (
  insn    : in std_logic_vector(31 downto 0);
  reglist : in std_logic_vector(APM_REGLIST_SZ-1 downto 0)
) return std_logic_vector is
  variable part03_00   : std_logic_vector(3 downto 0);
  variable part07_04   : std_logic_vector(3 downto 0);
  variable part11_08   : std_logic_vector(3 downto 0);
  variable part15_12   : std_logic_vector(3 downto 0);
  variable part03_00ui : integer;
  variable part03_00di : integer;
  variable part07_04ui : integer;
  variable part07_04di : integer;
  variable part11_08ui : integer;
  variable part11_08di : integer;
  variable part15_12ui : integer;
  variable part15_12di : integer;
  variable src4        : std_logic_vector(3 downto 0);
  variable src4ui        : integer;
  variable src4di        : integer;
  variable srcu        : std_logic_vector(1 downto 0);
  variable srcd        : std_logic_vector(1 downto 0);
  variable posu        : std_logic_vector(3 downto 0);
  variable posd        : std_logic_vector(3 downto 0);
  variable i           : integer;
begin
  part03_00 := reglist( 3 downto  0);  
  part07_04 := reglist( 7 downto  4);
  part11_08 := reglist(11 downto  8);
  part15_12 := reglist(15 downto 12);

  -- priority 0-3
  part03_00ui := 0;
L1u:  for i in 0 to 3 loop
    if part03_00(i) = '1' then
      part03_00ui := i;
      exit L1u;
    end if;
  end loop;  
  part03_00di := 3;
L1d:  for i in 3 downto 0 loop
    if part03_00(i) = '1' then
      part03_00di := i;
      exit L1d;
    end if;
  end loop;  

  -- priority 4-7
  part07_04ui := 0;
L2u:  for i in 0 to 3 loop
    if part07_04(i) = '1' then
      part07_04ui := i;
      exit L2u;
    end if;
  end loop;  
  part07_04di := 3;
L2d:  for i in 3 downto 0 loop
    if part07_04(i) = '1' then
      part07_04di := i;
      exit L2d;
    end if;
  end loop;  

  -- priority 8-11
  part11_08ui := 0;
L3u:  for i in 0 to 3 loop
    if part11_08(i) = '1' then
      part11_08ui := i;
      exit L3u;
    end if;
  end loop;  
  part11_08di := 3;
L3d:  for i in 3 downto 0 loop
    if part11_08(i) = '1' then
      part11_08di := i;
      exit L3d;
    end if;
  end loop;  

  -- priority 12-15
  part15_12ui := 0;
L4u:  for i in 0 to 3 loop
    if part15_12(i) = '1' then
      part15_12ui := i;
      exit L4u;
    end if;
  end loop;  
  part15_12di := 0;
L4d:  for i in 3 downto 0 loop
    if part15_12(i) = '1' then
      part15_12di := i;
      exit L4d;
    end if;
  end loop;  

  src4 := (others => '0');
  if part03_00 /= "0000" then
    src4(0) := '1';
  end if;
  if part07_04 /= "0000" then
    src4(1) := '1';
  end if;
  if part11_08 /= "0000" then
    src4(2) := '1';
  end if;
  if part15_12 /= "0000" then
    src4(3) := '1';
  end if;

  -- priority upper blocks
  src4ui := 0;
S4u:  for i in 0 to 3 loop
    if src4(i) = '1' then
      src4ui := i;
      exit S4u;
    end if;
  end loop;  
  src4di := 3;
S4d:  for i in 3 downto 0 loop
    if src4(i) = '1' then
      src4di := i;
      exit S4d;
    end if;
  end loop;  

  srcu := std_logic_vector(conv_unsigned(src4ui, 2));
  srcd := std_logic_vector(conv_unsigned(src4di, 2));
    
  posu(3 downto 2) := srcu;
  case srcu is
    when "11" => posu(1 downto 0) := std_logic_vector(conv_unsigned(part15_12ui, 2));
    when "10" => posu(1 downto 0) := std_logic_vector(conv_unsigned(part11_08ui, 2));
    when "01" => posu(1 downto 0) := std_logic_vector(conv_unsigned(part07_04ui, 2));
    when "00" => posu(1 downto 0) := std_logic_vector(conv_unsigned(part03_00ui, 2));
    when others => null;
  end case;
  posd(3 downto 2) := srcd;
  case srcd is
    when "11" => posd(1 downto 0) := std_logic_vector(conv_unsigned(part15_12di, 2));
    when "10" => posd(1 downto 0) := std_logic_vector(conv_unsigned(part11_08di, 2));
    when "01" => posd(1 downto 0) := std_logic_vector(conv_unsigned(part07_04di, 2));
    when "00" => posd(1 downto 0) := std_logic_vector(conv_unsigned(part03_00di, 2));
    when others => null;
  end case;

  if insn(ADE_UID_U) = '1' then
    return posu; -- Increment regorder [0-15]
  else
    return posd; -- Decrement regorder [15-0]
  end if;

  return posu;
end;

function lin_convint (
  op   : in std_logic_vector
) return integer is
variable tmp : integer;
begin
  tmp := 0;
-- pragma translate_off
    if not (is_x(op)) then
-- pragma translate_on
      tmp := conv_integer(op);
-- pragma translate_off
    end if;
-- pragma translate_on
  return tmp;
end;

type fpu_state is (start, get_operand, pre_norm, add_sub, post_norm,
                   rnd_norm, hold_val);

constant LIN_FOUR    : std_logic_vector(31 downto 0) := "00000000000000000000000000000100";

constant LIN_MINFOUR : std_logic_vector(31 downto 0) := "11111111111111111111111111111100";

procedure als_offsets (
  insn : in std_logic_vector(31 downto 0);
  startoff  : inout std_logic_vector(31 downto 0);
  endoff    : inout std_logic_vector(31 downto 0);
  incval    : inout std_logic_vector(31 downto 0)
) is
variable mode : std_logic_vector(1 downto 0);
variable regnum_mul4 : std_logic_vector(31 downto 0);
begin
  mode := insn(ADE_PAB_U)&insn(ADE_UID_U);
    
  startoff := (others => '0');
  endoff   := (others => '0');
  incval   := (others => '0');

  -- LRM/STM: Increment after  (regorder [0-15],start:+0,end(onwb):+4) :ldmia|stmia <rn>,{<reglist>}
  -- LRM/STM: Increment before (regorder [0-15],start:+4,end(onwb):+0) :ldmib|stmib <rn>,{<reglist>}
  -- LRM/STM: Decrement after  (regorder [15-0],start:-0,end(onwb):-4) :ldmda|stmda <rn>,{<reglist>}
  -- LRM/STM: Decrement before (regorder [15-0],start:-4,end(onwb):-0) :ldmdb|stmdb <rn>,{<reglist>}
  case mode is
    when "01" => incval := LIN_FOUR   ; startoff := (others=> '0'); endoff := LIN_FOUR;       -- increment after
    when "11" => incval := LIN_FOUR   ; startoff := LIN_FOUR      ; endoff := (others=> '0'); -- increment before
    when "00" => incval := LIN_MINFOUR; startoff := (others=> '0'); endoff := LIN_MINFOUR;    -- decrement after
    when "10" => incval := LIN_MINFOUR; startoff := LIN_MINFOUR   ; endoff := (others=> '0'); -- decrement before
    when others => 
  end case;
   
end;

constant APM_RREAL_PC : std_logic_vector(4 downto 0) := "01111";

function apc_is_branch(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.wr.wrop_rdvalid = '1') and
       (pctrl.wr.wrop_rd = APM_RREAL_PC) then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_memload(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_mem(pctrl) then
    if pctrl.me.meop_param.read = '1' then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_straddr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.me.meop_enable = '1') and
       (pctrl.me.meop_param.read = '0') and
       (pctrl.me.meop_param.addrin = '1') then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_strdata(
  pctrl   : apc_pctrl
) return boolean  is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.me.meop_enable = '1') and
       (pctrl.me.meop_param.read = '0') and
       (pctrl.me.meop_param.writedata = '1') then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

function apc_is_rdlocked(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) and
     (pctrl.me.meop_enable = '1') and
     (pctrl.me.meop_param.read = '1') and
     (pctrl.wr.wrop_rdvalid = '1') then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_rdlocked_by (
  rd    : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  pctrl : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if (pctrl.wr.wrop_rd = rd) and apc_is_rdlocked(pctrl) then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_rdfromalu(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if  apc_is_valid(pctrl) and
     (not apc_is_memload(pctrl)) and 
     (pctrl.wr.wrop_rdvalid = '1') then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_rswillshieft(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    -- shiefter output used
    if pctrl.rs.rsop_op2_src = apc_opsrc_through or
       pctrl.rs.rsop_buf2_src = apc_bufsrc_through then
      -- shiefter does something
      if (pctrl.rs.rsop_styp = ash_styp_simm) or
         (pctrl.rs.rsop_styp = ash_styp_sreg) then
        if not (pctrl.rs.rsop_sdir = ash_sdir_snone) then
          tmp := true;
        end if;
      end if;
    end if;
  end if;
  return tmp;
end;

function apc_is_exwillsetcpsr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := apc_is_valid(pctrl) and
        (pctrl.ex.exop_setcpsr = '1') ;
  return tmp;
end;

function apc_is_usecpsr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if apc_is_rswillshieft(pctrl) then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);

function apc_is_flush(
  stgid : std_logic_vector(2 downto 0);
  flushid : std_logic_vector(2 downto 0)
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if not (stgid = flushid) then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_valid (
  pctrl : apc_pctrl
) return boolean;

-- check weather branch (reg/mem)
function apc_is_branch(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------
-- pctrl predicate: mem op 

-- check weather mestg active
function apc_is_mem(
  pctrl   : apc_pctrl
) return boolean;

-- check weather mestg load
function apc_is_memload(
  pctrl   : apc_pctrl
) return boolean;

-- check weather str addr (next pctrl will be store data) 
function apc_is_straddr(
  pctrl   : apc_pctrl
) return boolean;

-- check weather str data (prev pctrl was be store addr) 
function apc_is_strdata(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------
-- pctrl predicate: register locking 

-- check weather it is a mem ldr
function apc_is_rdlocked(
  pctrl   : apc_pctrl
) return boolean;

-- check weather app_is_rdlocked() + rd compare
function apc_is_rdlocked_by (
  rd    : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  pctrl : apc_pctrl
) return boolean;

-- check weather wrstg rd data come from alu
function apc_is_rdfromalu(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------
-- pctrl predicate: cpsr locking 

-- check weather rsstg is used
function apc_is_rswillshieft(
  pctrl   : apc_pctrl
) return boolean;

-- check weather cpsr will be modified 
function apc_is_exwillsetcpsr(
  pctrl   : apc_pctrl
) return boolean;

-- check weather cpsr is used 
function apc_is_usecpsr(
  pctrl   : apc_pctrl
) return boolean;

-------------------------------------------------------------------------------

-- check weather stg should flush
function apc_is_flush(
  stgid : std_logic_vector(2 downto 0);
  flushid : std_logic_vector(2 downto 0)
) return boolean;

end armpctrl;

package body armpctrl is

function apc_is_valid (
  pctrl : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if pctrl.valid = '1' then
    tmp := true;
  end if;
  return tmp;
end;

function apc_is_mem(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if pctrl.me.meop_enable = '1' then
      tmp := true;
    end if;
  end if;
  return tmp;
end;

constant ADE_OP_U : integer := 24;

constant ADE_OP_D : integer := 21;

procedure acm_initmempctrl (
  pctrl : inout apc_pctrl;
  r1_src    : inout acm_regsrc;  -- (micro.r1)
  r2_src    : inout acm_regsrc;  -- (micro.r2)
  rd_src    : inout acm_rdsrc;   -- (pctrl.wr.wrop_rd)
  mem : in acm_ctrlmemout
);
  
-- general ldm stm control
type acm_ctrlmult_in is record
  ctrlmemo  : acm_ctrlmemout;
  ival  : std_logic_vector(31 downto 0);
  soff  : std_logic_vector(31 downto 0);
  eoff  : std_logic_vector(31 downto 0);
  reglist  : std_logic_vector(APM_REGLIST_SZ-1 downto 0);
  mem   : std_logic;                    -- mem still present in pipeline
  dabort   : std_logic;                    -- mem still present in pipeline
end record;


end armcmd;

package body armcmd is

procedure acm_initmempctrl (
  pctrl : inout apc_pctrl;
  r1_src    : inout acm_regsrc;  -- (micro.r1)
  r2_src    : inout acm_regsrc;  -- (micro.r2)
  rd_src    : inout acm_rdsrc;   -- (pctrl.wr.wrop_rd)
  mem : in acm_ctrlmemout
) is
begin

  pctrl.data1 := mem.data1; -- immidiate 1 
  pctrl.data2 := mem.data2; -- immidiate 2

  -- rrstg:
  r1_src := mem.r1_src;     -- (micro.r1)
  r2_src := mem.r2_src;     -- (micro.r2)
  rd_src := mem.rd_src;     -- (pctrl.wr.wrop_rd)
  
  -- rsstg: 
  pctrl.rs.rsop_op1_src := mem.rsop_op1_src;    -- EXSTG operand1 source 
  pctrl.rs.rsop_op2_src := mem.rsop_op2_src;    -- EXSTG operand1 source 
  pctrl.rs.rsop_buf1_src := mem.rsop_buf1_src;  -- RSSTG buffer1 source 
  pctrl.rs.rsop_buf2_src := mem.rsop_buf2_src;  -- RSSTG buffer2 source 
  
  -- exstg:
  pctrl.ex.exop_data_src := mem.exop_data_src;  -- EXSTG pctrl.data1 source 
  pctrl.ex.exop_buf_src := mem.exop_buf_src;    -- ESSTG buffer source      
  
  -- mestg:
  pctrl.me.meop_param := mem.meop_param; 
  pctrl.me.meop_enable:= mem.meop_enable; 

end;

procedure als_LSV4AM_init_size(
  insn : in std_logic_vector(31 downto 0);
  pctrl : inout apc_pctrl
) is
begin
  if insn(ADE_LSV4AM_SIGNED) = '1' then
    pctrl.me.meop_param.signed := '1';
  else
    pctrl.me.meop_param.signed := '0';
  end if;

  if insn(ADE_LSV4AM_HALF) = '1' then
    pctrl.me.meop_param.size  := lmd_half;
  else
    pctrl.me.meop_param.size  := lmd_byte;
  end if;
end;

constant ADE_OP_ADD : std_logic_vector(3 downto 0) := "0100";

constant ADE_OP_SUB : std_logic_vector(3 downto 0) := "0010";

procedure als_LDSTAMxLSV4AM_init_addsub(
  insn : in std_logic_vector(31 downto 0);
  pctrl : inout apc_pctrl
) is
begin
  if insn(ADE_LDSTAMxLSV4AM_ADD) = '1' then
    pctrl.ex.exop_aluop := ADE_OP_ADD;
  else
    pctrl.ex.exop_aluop := ADE_OP_SUB;
  end if;
end;

procedure als_LDSTAM_init_size(
  insn : in std_logic_vector(31 downto 0);
  pctrl : inout apc_pctrl
);

-- Init size and signed for LSV4AM
procedure als_LSV4AM_init_size(
  insn : in std_logic_vector(31 downto 0);
  pctrl : inout apc_pctrl
);

-- Init address calc exop
procedure als_LDSTAMxLSV4AM_init_addsub(
  insn : in std_logic_vector(31 downto 0);
  pctrl : inout apc_pctrl
);

-------------------------------------------------------------------------------
-- multiple load / store

-- Count leading zeros
function als_getnextpos (
  insn    : in std_logic_vector(31 downto 0);
  reglist : in std_logic_vector(APM_REGLIST_SZ-1 downto 0)
) return std_logic_vector;

-- get inc/decrement offsets
procedure als_offsets (
  insn : in std_logic_vector(31 downto 0);
  startoff  : inout std_logic_vector(31 downto 0);
  endoff    : inout std_logic_vector(31 downto 0);
  incval    : inout std_logic_vector(31 downto 0)
);

-------------------------------------------------------------------------------

end armldst;

package body armldst is

procedure als_LDSTAM_init_size(
  insn : in std_logic_vector(31 downto 0);
  pctrl : inout apc_pctrl
) is
begin
  -- unsigned byte / word
  if insn(ADE_LDSTAM_UBYTE) = '1' then
    pctrl.me.meop_param.size  := lmd_byte;
    pctrl.me.meop_param.signed := '0';
  else
    pctrl.me.meop_param.size  := lmd_word;
    pctrl.me.meop_param.signed := '1';
  end if;
end;

constant APM_REG_PC     : std_logic_vector(3 downto 0) := "1111";

constant ADE_OP_ORR : std_logic_vector(3 downto 0) := "1100";

type istatetype is (idle, trans, streaming, stop);

constant APM_USR : std_logic_vector(4 downto 0) := "10000";

constant APM_SYS : std_logic_vector(4 downto 0) := "11111";

constant APM_SVC : std_logic_vector(4 downto 0) := "10011";

constant APM_ABT : std_logic_vector(4 downto 0) := "10111";

constant APM_UND : std_logic_vector(4 downto 0) := "11011";

constant APM_FIQ : std_logic_vector(4 downto 0) := "10001";

constant APM_IRQ : std_logic_vector(4 downto 0) := "10010";

function apm_bankreg(
  mode : in std_logic_vector(4 downto 0);
  addr : in std_logic_vector
) return std_logic_vector is
variable tmp  : std_logic_vector(addr'high+1 downto 0);  -- +1: return is 5bits
variable bank : std_logic_vector(addr'high+1 downto 0);  
begin
  tmp := "0"&addr(addr'high downto 0);
  bank := "0"&addr(addr'high downto 0);
  case mode is
    when APM_USR => 
    when APM_SYS => 
    when APM_SVC =>
      bank := "1100" & not addr(0);
    when APM_ABT => 
      bank := "1101" & not addr(0);
    when APM_UND => 
      bank := "1110" & not addr(0);
    when APM_FIQ => 
      if addr(3) = '1' then
        bank(4 downto 3) := "10";
        tmp(4 downto 3) := "10";
      end if;
    when APM_IRQ => 
      bank := "1111" & not addr(0);
    when others => 
  end case;
  case addr(3 downto 0) is
    when "1101"|"1110" => tmp := bank;
    when others => 
  end case;
  return tmp;
end;

constant ADE_REGLIST_U  : integer := 15;

constant ADE_REGLIST_D  : integer := 0;

function lin_decode(
  v : std_logic_vector
) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
  res := (others => '0');
-- pragma translate_off
  i := 0;
  if not is_x(v) then
-- pragma translate_on
    i := conv_integer(unsigned(v));
    res(i) := '1';
-- pragma translate_off
  else
    res := (others => 'X');
  end if;
-- pragma translate_on
  return(res);
end;

constant lin_log2x : lin_log2arr := (1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

function lin_countzero(
  data : in    std_logic_vector
) return std_logic_vector is
variable z02 : std_logic_vector((data'length/2)-1 downto 0);
variable z04 : std_logic_vector((data'length/4)-1 downto 0);
variable d04 : std_logic_vector(3 downto 0);
variable z08 : std_logic_vector((data'length/8)-1 downto 0);
variable d08 : std_logic_vector(7 downto 0);
variable z16 : std_logic_vector((data'length/16)-1 downto 0);
variable d16 : std_logic_vector(15 downto 0);
variable z32 : std_logic_vector((data'length/32)-1 downto 0);
variable d32 : std_logic_vector(31 downto 0);
variable z64 : std_logic_vector((data'length/64)-1 downto 0);
variable d64 : std_logic_vector(63 downto 0);
variable res : std_logic_vector(lin_log2x(data'length)-1 downto 0);
variable length : integer;
variable tmp : integer;
begin

  res := (others => '0');
  z32 := (others => '0');
  z02 := (others => '0');
  z04 := (others => '0');
  length := data'length;
  
  if (length / 2) >= 1 then
    tmp := 0;
L02:
    for i in (length/2)-1 downto 0 loop
      tmp := i;
      if    (data((i*2)+0) = '1') then
        z02(i) := '1';
        exit L02;
      elsif (data((i*2)+1) = '1') then
        z02(i) := '0';
        exit L02;
      else
        z02(i) := '0';
      end if;
    end loop;  -- i
    if (length = 2) then
      res(0) := z02(tmp);
    end if;
  end if;
  
  if (length / 4) >= 1 then
    tmp := 0;
L04:
    for i in (length/4)-1 downto 0 loop
      tmp := i;
      d04 := data((i*4)+3 downto i*4);
      z04(i) := '1';
      if    not (d04(3 downto 2) = "00") then
        z04(i) := '1';
        res(0) := z02(i*2);
        exit L04;
      elsif not (d04(1 downto 0) = "00") then
        z04(i) := '0';
        res(0) := z02((i*2)+1);
        exit L04;
      else
        z04(i) := '0';
      end if;
    end loop;  -- i
    if (length = 4) then
      res(1) := z04(tmp);
    end if;
  end if;
  
  if (length / 8) >= 1 then
    tmp := 0;
L08:
    for i in (length/8)-1 downto 0 loop
      tmp := i;
      d08 := data((i*8)+7 downto i*8);
      z08(i) := '1';
      if    not (d08(7 downto 4) = "0000") then
        z08(i) := '1';
        res(1) := z04(i*2);
        exit L08;
      elsif not (d08(3 downto 0) = "0000") then
        z08(i) := '0';
        res(1) := z04((i*2)+1);
        exit L08;
      else
        z08(i) := '0';
      end if;
    end loop;  -- i
    if (length = 8) then
      res(2) := z08(tmp);
    end if;
  end if;
  
  if (length / 16) >= 1 then
    tmp := 0;
L16:
    for i in (length/16)-1 downto 0 loop
      tmp := i;
      d16 := data((i*16)+15 downto i*16);
      z16(i) := '1';
      if    not (d16(15 downto 8) = "00000000") then
        z16(i) := '1';
        res(2) := z08(i*2);
        exit L16;
      elsif not (d16(7 downto 0) = "00000000") then
        z16(i) := '0';
        res(2) := z08((i*2)+1);
        exit L16;
      else
        z16(i) := '0';
      end if;
    end loop;  -- i
    if (length = 16) then
      res(3) := z16(tmp);
    end if;
  end if;

  if (length / 32) >= 1 then
    tmp := 0;
L32:
    for i in (length/32)-1 downto 0 loop
      tmp := i;
      d32 := data((i*32)+31 downto i*32);
      z32(i) := '1';
      if    not (d32(31 downto 16) = "0000000000000000") then
        z32(i) := '1';
        res(3) := z16(i*2);
        exit L32;
      elsif not (d32(15 downto 0) = "0000000000000000") then
        z32(i) := '0';
        res(3) := z16((i*2)+1);
        exit L32;
      else
        z32(i) := '0';
      end if;
    end loop;  -- i
    if (length = 32) then
      res(4) := z32(tmp);
    end if;
  end if;
  
  if (length / 64) >= 1 then
    tmp := 0;
L64:
    for i in (length/64)-1 downto 0 loop
      tmp := i;
      d64 := data((i*64)+63 downto i*64);
      z64(i) := '1';
      if    not (d64(63 downto 32) = "00000000000000000000000000000000") then
        z64(i) := '1';
        res(4) := z32(i*2);
        exit L64;
      elsif not (d64(31 downto 0) = "00000000000000000000000000000000") then
        z64(i) := '0';
        res(4) := z32((i*2)+1);
        exit L64;
      else
        z64(i) := '0';
      end if;
    end loop;  -- i
    if (length = 64) then
      res(5) := z64(tmp);
    end if;
  end if;

  return res;
end;

procedure lin_adder(
  op1   : in std_logic_vector(31 downto 0);
  op2   : in std_logic_vector(31 downto 0);
  carry : in std_logic;
  sub   : in std_logic;
  sum   : out std_logic_vector(31 downto 0)
) is
begin
-- pragma translate_off
    if not (is_x(op1) or is_x(op2) or is_x(carry)) then
-- pragma translate_on
      if sub = '1' then
        sum := op1 - op2 - carry;
      else
        sum := op1 + op2 + carry;
      end if;
-- pragma translate_off
    else
      sum := (others => 'X');
    end if;
-- pragma translate_on

end;

constant log2  : log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

procedure lin_incdec(
  source : in    std_logic_vector;
  dest   : inout std_logic_vector;
  do     : in    std_logic;
  inc    : in    std_logic
);
  
-- convert std_logic_vector to integer
function lin_convint(
  op   : in std_logic_vector
) return integer;

-- set bit integer(v)
function lin_decode(
  v : std_logic_vector
) return std_logic_vector;

-- pos of first '1' from left
function lin_countzero(
  data : in    std_logic_vector
) return std_logic_vector;

-- adder with carryin
procedure lin_adder(
  op1   : in std_logic_vector(31 downto 0);
  op2   : in std_logic_vector(31 downto 0);
  carry : in std_logic;
  sub   : in std_logic;
  sum   : out std_logic_vector(31 downto 0)
);

----------------------------------------------------------------------------
-- log2 tables
----------------------------------------------------------------------------

type lin_log2arr is array(1 to 64) of integer;
constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others => 6);
constant lin_log2x : lin_log2arr := (1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others => 6);

end int;

package body int is
  
procedure lin_incdec(
  source : in    std_logic_vector;
  dest   : inout std_logic_vector;
  do     : in    std_logic;
  inc    : in    std_logic
) is
variable tmp : std_logic_vector(source'range);
begin

  tmp := (others => '0');
-- pragma translate_off
    if not is_x(source) then
-- pragma translate_on
      if inc = '1' then
        tmp := source(source'range) + 1;
      else
        tmp := source(source'range) - 1;
      end if;
-- pragma translate_off
    else
      tmp := (others => 'X');
    end if;
-- pragma translate_on

    if (do) = '1' then
      dest := tmp;
    end if;

end;

type adg_dbgaluop is (
  adg_opand,
  adg_opeor,
  adg_opsub,
  adg_oprsb,
  adg_opadd,
  adg_opadc,
  adg_opsbc,
  adg_oprsc,
  adg_optst,
  adg_opteq,
  adg_opcmp,
  adg_opcmn,
  adg_oporr,
  adg_opmov,
  adg_opbic,
  adg_opmvn,
  adg_opinvalid
);

constant ADE_OP_AND : std_logic_vector(3 downto 0) := "0000";

constant ADE_OP_EOR : std_logic_vector(3 downto 0) := "0001";

constant ADE_OP_RSB : std_logic_vector(3 downto 0) := "0011";

constant ADE_OP_ADC : std_logic_vector(3 downto 0) := "0101";

constant ADE_OP_SBC : std_logic_vector(3 downto 0) := "0110";

constant ADE_OP_RSC : std_logic_vector(3 downto 0) := "0111";

constant ADE_OP_TST : std_logic_vector(3 downto 0) := "1000";

constant ADE_OP_TEQ : std_logic_vector(3 downto 0) := "1001";

constant ADE_OP_CMP : std_logic_vector(3 downto 0) := "1010";

constant ADE_OP_CMN : std_logic_vector(3 downto 0) := "1011";

constant ADE_OP_MOV : std_logic_vector(3 downto 0) := "1101";

constant ADE_OP_BIC : std_logic_vector(3 downto 0) := "1110";

constant ADE_OP_MVN : std_logic_vector(3 downto 0) := "1111";

function adg_todbgaluop (
  mode : std_logic_vector(3 downto 0)
) return adg_dbgaluop is
  variable tmp : adg_dbgaluop;
begin

  tmp := adg_opinvalid;

  case mode is
    when ADE_OP_AND => tmp := adg_opand;
    when ADE_OP_EOR => tmp := adg_opeor;
    when ADE_OP_SUB => tmp := adg_opsub;
    when ADE_OP_RSB => tmp := adg_oprsb;
    when ADE_OP_ADD => tmp := adg_opadd;
    when ADE_OP_ADC => tmp := adg_opadc;
    when ADE_OP_SBC => tmp := adg_opsbc;
    when ADE_OP_RSC => tmp := adg_oprsc;
    when ADE_OP_TST => tmp := adg_optst;
    when ADE_OP_TEQ => tmp := adg_opteq;
    when ADE_OP_CMP => tmp := adg_opcmp;
    when ADE_OP_CMN => tmp := adg_opcmn;
    when ADE_OP_ORR => tmp := adg_oporr;
    when ADE_OP_MOV => tmp := adg_opmov;
    when ADE_OP_BIC => tmp := adg_opbic;
    when ADE_OP_MVN => tmp := adg_opmvn;
    when others => 
  end case;
  return tmp;
end;

function adg_todbgpmode (
  mode : std_logic_vector(4 downto 0)
) return adg_dbgpmode;

-------------------------------------------------------------------------------

-- dbg: readable aluop 
type adg_dbgaluop is (
  adg_opand,
  adg_opeor,
  adg_opsub,
  adg_oprsb,
  adg_opadd,
  adg_opadc,
  adg_opsbc,
  adg_oprsc,
  adg_optst,
  adg_opteq,
  adg_opcmp,
  adg_opcmn,
  adg_oporr,
  adg_opmov,
  adg_opbic,
  adg_opmvn,
  adg_opinvalid
);

-- Convert to readable aluop enum
function adg_todbgaluop (
  mode : std_logic_vector(3 downto 0)
) return adg_dbgaluop;

-- pragma translate_on

end armdebug;

package body armdebug is

-- pragma translate_off
  
function adg_todbgpmode (
  mode : std_logic_vector(4 downto 0)
) return adg_dbgpmode is
  variable tmp : adg_dbgpmode;
begin

  tmp := adg_invalid;

  case mode is
    when APM_USR => tmp := adg_usr;
    when APM_SYS => tmp := adg_sys;
    when APM_SVC => tmp := adg_svc;
    when APM_ABT => tmp := adg_abt;
    when APM_UND => tmp := adg_und;
    when APM_IRQ => tmp := adg_irq;
    when APM_FIQ => tmp := adg_fiq;
    when others => null;
  end case;
  return tmp;
end;