/tmp/build_html/vhdl/arm/armiu_destg.vhd : l8arm - synthesizable ARM v4 vhdl model.

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-- $(lic)
-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
use work.memdef.all;
use work.int.all;
use work.armdecode.all;
use work.arm_comp.all;

entity armiu_destg is
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_destg_typ_in;
    o       : out armiu_destg_typ_out
    );
end armiu_destg;

architecture rtl of armiu_destg is

  type armiu_destg_tmp_type is record
    o : armiu_destg_typ_out;
    commit : std_logic;
    decinsn : ade_deinsn;
  end record;
  type armiu_destg_reg_type is record
    decinsn : ade_deinsn;
    id      : std_logic_vector(2 downto 0);
  end record;
  type armiu_destg_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_destg_tmp_type;
     -- pragma translate_on
  end record;
  signal r, c       : armiu_destg_reg_type;
  signal rdbg, cdbg : armiu_destg_dbg_type;

begin  
    
  p0: process (clk, rst, r, i  )
    variable v    : armiu_destg_reg_type;
    variable t    : armiu_destg_tmp_type;
    variable vdbg : armiu_destg_dbg_type;
  begin 
    
    -- $(init(t:armiu_destg_tmp_type))
    
    v := r;
    t.commit := not i.flush_v;
      
    t.decinsn.insn.pc_8 := i.fromFE_insn_v.pc_vir;
    t.decinsn.insn.insn := i.fromFE_insn_r.insn;
    t.decinsn.insn.insn := lmd_convert ( t.decinsn.insn.insn, CFG_BO_INSN, CFG_BO_PROC );
    t.decinsn.insn.decinsn := ade_decode_v4 ( t.decinsn.insn.insn );
    ade_decode_amode ( t.decinsn.insn.insn, t.decinsn.insn.am );
    t.decinsn.insn.valid := i.fromFE_insn_r.valid;
    t.decinsn.insn.id := r.id;
    
    if i.fromFE_insn_r.trap = '1' then
      t.decinsn.insn.decinsn := type_arm_nop;
      t.decinsn.insn.valid := '1';
      t.decinsn.trap := '1';
    end if;
    
    t.decinsn.insn.insntyp := ade_typmisc;
    case t.decinsn.insn.decinsn is
      when type_arm_invalid => 
      when type_arm_nop => 
      when type_arm_mrs | 
           type_arm_msr => 
      when type_arm_bx => 
      when type_arm_mul => 
        t.decinsn.insn.insntyp := ade_typalu;
      when type_arm_mla => 
        t.decinsn.insn.insntyp := ade_typalu;
      when type_arm_sumull => 
        t.decinsn.insn.insntyp := ade_typalu;
      when type_arm_sumlal => 
        t.decinsn.insn.insntyp := ade_typalu;
      when type_arm_teq |  
           type_arm_cmn |  
           type_arm_tst |  
           type_arm_cmp => 
        t.decinsn.insn.insntyp := ade_typalu;
      when type_arm_and |
           type_arm_sub |
           type_arm_eor |
           type_arm_rsb |
           type_arm_add |
           type_arm_orr |
           type_arm_bic |
           type_arm_mov |
           type_arm_mvn | 
           type_arm_sbc |  
           type_arm_adc |  
           type_arm_rsc =>
        t.decinsn.insn.insntyp := ade_typalu;
      when type_arm_str1 |
           type_arm_str2 |
           type_arm_str3 |
           type_arm_strhb =>
        t.decinsn.insn.insntyp := ade_typmem;
      when type_arm_ldr1 |
           type_arm_ldrhb =>
        t.decinsn.insn.insntyp := ade_typmem;
      when type_arm_stm =>              
        t.decinsn.insn.insntyp := ade_typmem;
      when type_arm_ldm =>              
        t.decinsn.insn.insntyp := ade_typmem;
      when type_arm_b =>
      when type_arm_swp => 
        t.decinsn.insn.insntyp := ade_typmem;
      when type_arm_stc =>
        t.decinsn.insn.insntyp := ade_typcp;
      when type_arm_ldc =>
        t.decinsn.insn.insntyp := ade_typcp;
      when type_arm_mrc |
           type_arm_mcr =>
        t.decinsn.insn.insntyp := ade_typcp;
      when type_arm_cdp =>
        t.decinsn.insn.insntyp := ade_typcp;
      when type_arm_swi =>
      when type_arm_undefined =>
      when others => 
    end case;

    -- pipeline flush
    if not (t.commit = '1') then
      t.decinsn.insn.valid := '0';
    end if;

    -- pipeline step
    if i.pstate.hold_r.hold = '0' then
      if i.pstate.nextinsn_v = '1' then
        v.decinsn := t.decinsn;
        v.decinsn.insn.pc_8 := i.fromFE_insn_v.pc_vir;
        v.decinsn.insn.id := r.id;
        lin_incdec(r.id,v.id,'1','1');
      end if;
    end if;
    
    t.o.toDR_insn_r := r.decinsn;
    t.o.toDR_insn_v := v.decinsn;
    
    -- reset
    if ( rst = '0' ) then
      v.decinsn.insn.valid := '0';
      v.id := (others => '0');
    end if;
    
    c <= v;
    
    o <= t.o;
    
    -- pragma translate_off
    vdbg := rdbg;
    vdbg.dbg := t;
    cdbg <= vdbg;
    -- pragma translate_on  
    
  end process p0;
    
  pregs : process (clk, c)
  begin
    if rising_edge(clk) then
      r <= c;
      -- pragma translate_off
      rdbg <= cdbg;
      -- pragma translate_on
    end if;
  end process;
  
end rtl;

File /tmp/build_html/vhdl/arm/armiu_destg.vhd

Enum astates defined in /tmp/build_html/vhdl/sparc/mmu_acache.vhd

type astates is (idle, dcache, icache, mmu);

Enum rdatatype defined in /tmp/build_html/vhdl/sparc/mmu_icache.vhd

type rdatatype is (itag, idata, memory);

Type cli_hold defined in /tmp/build_html/vhdl/core/libs/corelib.vhd

type cli_hold is record
   hold : std_logic; -- hold
   dhold : std_logic; -- dcache hold
   ihold : std_logic; -- icache hold
end record;

Enum mcycletype defined in /tmp/build_html/vhdl/peripherals/mem/sdmctrl.vhd

type mcycletype is (midle, active, leadout);

Constant zero defined in /tmp/build_html/vhdl/sparc/pci_gr.vhd

constant zero : std_logic_vector(31 downto 0) := (others =>

Type apm_excpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_excpsr is record
   n      : std_logic;                  -- negative
   z      : std_logic;                  -- zero
   c      : std_logic;                  -- carry
   v      : std_logic;                  -- overflow
   -- extensions
   -- fext   : std_logic_vector(3 downto 0);  -- cpsr(27:24)
   -- xext   : std_logic_vector(7 downto 0);  -- cpsr(15:8)
   -- sext   : std_logic_vector(7 downto 0);  -- cpsr(23:16)
end record;

Type apm_wrcpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_wrcpsr is record
   i      : std_logic;                  -- [7] irq
   f      : std_logic;                  -- [6] fiq
   t      : std_logic;                  -- [5] thumb
   mode   : std_logic_vector(4 downto 0);
-- pragma translate_off
--   dbgmode  : aba_atyp_dbgpmode;       -- readable pmode for dbg
-- pragma translate_on
end record;

Type apm_cpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_cpsr is record
   ex : apm_excpsr;
   wr : apm_wrcpsr;
end record;

Enum ade_insntyp defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_insntyp is (
  ade_typmem,
  ade_typalu,
  ade_typmisc,
  ade_typcp
);

Enum ade_decinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_decinsn is (
  type_arm_invalid,type_arm_nop,    type_arm_mrs,    type_arm_bx,    type_arm_mul,   type_arm_mla,
  type_arm_swp,    type_arm_sumull, type_arm_sumlal, type_arm_strhb, type_arm_ldrhb, type_arm_and,
  type_arm_sub,    type_arm_eor,    type_arm_rsb,    type_arm_add,   type_arm_sbc,   type_arm_adc, 
  type_arm_msr,    type_arm_teq,    type_arm_cmn,    type_arm_tst,   type_arm_cmp,   type_arm_orr, 
  type_arm_mov,    type_arm_mvn,    type_arm_str1,   type_arm_str2,  type_arm_str3,  type_arm_ldr1,
  type_arm_stm,    type_arm_ldm,    type_arm_b,      type_arm_swi,   type_arm_cdp,   type_arm_mrc,
  type_arm_mcr,    type_arm_stc,    type_arm_ldc,    type_arm_rsc,   type_arm_bic,   type_arm_undefined
);

Enum ade_DAPRAM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_DAPRAM is (
  ade_DAPRAM_simm,       -- OP2 shieft with imm 
  ade_DAPRAM_sreg,       -- OP2 shieft with reg 
  ade_DAPRAM_immrot      -- OP2 immidiate rotated
);

Enum ade_LDSTAMxLSV4AM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_LDSTAMxLSV4AM is (
  ade_LDSTAMxLSV4AM_imm,  -- addr v1 imm
                          -- addr v4 imm
  ade_LDSTAMxLSV4AM_reg   -- addr v1 reg (shieft with imm)
                          -- addr v4 reg
);

Enum icycletype defined in /tmp/build_html/vhdl/peripherals/mem/sdmctrl.vhd

type icycletype is (iidle, pre, ref1, ref2, lmode, finish);

Enum ade_pos defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_pos is (
  ade_pre,      -- pre indexed
  ade_post      -- post indexed
);

Enum ash_sdir defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd

type ash_sdir is (
  ash_sdir_snone,    -- no shieft
  ash_sdir_slsl,     -- LSL #: logical shieft left 
  ash_sdir_slsr,     -- LSR #: logical shieft righ
  ash_sdir_sasr,     -- ASR #: arithmetic shieft left
  ash_sdir_sror,     -- ROR #: rotate 
  ash_sdir_srrx      -- RRX #: rotate 1 with carry
);

Type ade_amode defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_amode is record
  DAPRAM_typ           : ade_DAPRAM;
  LDSTAM_typ           : ade_LDSTAMxLSV4AM;
  LSV4AM_typ           : ade_LDSTAMxLSV4AM;
  LDSTAMxLSV4AM_pos    : ade_pos;
  DAPRAMxLDSTAM_sdir   : ash_sdir;
  LDSTAMxLSV4AM_uacc   : std_logic;
  LDSTAMxLSV4AM_wb     : std_logic;
end record;

Type ade_insn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_insn is record
  pc_8    : std_logic_vector(31 downto 0);
  insn    : std_logic_vector(31 downto 0);
  insntyp : ade_insntyp;
  decinsn : ade_decinsn;
  am      : ade_amode;
  valid   : std_logic;
  id      : std_logic_vector(2 downto 0);
end record;

Type apc_rrstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rrstg is record
  -- operations
  dummy : std_logic;
end record;

Enum apc_rsop_opsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsop_opsrc is (
  apc_opsrc_through,
  apc_opsrc_buf,
  apc_opsrc_alures,
  apc_opsrc_none
);

Enum apc_rsop_bufsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsop_bufsrc is (
  apc_bufsrc_none,
  apc_bufsrc_through,
  apc_bufsrc_alures
);

Enum ash_styp defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd

type ash_styp is (
  ash_styp_none,  -- no shieft
  ash_styp_immrot,-- DAPRAM: OP2 immidiate rotated
  ash_styp_simm,  -- DAPRAM: OP2 shieft with imm, LDSTAM: addr v1 reg (adm_LDSTAM_reg) 
  ash_styp_sreg   -- DAPRAM: OP2 shieft with reg  
);

Enum txfsmtype defined in /tmp/build_html/vhdl/sparc/dcom_uart.vhd

type txfsmtype is (idle, data, stopbit);

Type apc_rsstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsstg is record
  -- operations
  rsop_op1_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_op2_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source
  rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source
  rsop_styp     : ash_styp;        -- RSSTG shieft op
  rsop_sdir     : ash_sdir;        -- RSSTG shieft dir
  -- data
  rs_shieftcarryout : std_logic;   -- RSSTG shiefter carry out
end record;

Enum apc_exop_datasrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exop_datasrc is (
  apc_datasrc_aluout,
  apc_datasrc_buf,
  apc_datasrc_none
);

Enum apc_exop_bufsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exop_bufsrc is (
  apc_exbufsrc_none,
  apc_exbufsrc_aluout,
  apc_exbufsrc_op1
);

Enum cpins_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type cpins_type is (none, cpop, load, store);

Type apc_exstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exstg is record
  -- operations
  exop_aluop    : std_logic_vector(3 downto 0);  -- EXSTG alu operation
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source
  exop_setcpsr  : std_logic;         -- EXSTG set cpsr
  -- data                                   
  ex_cpsr : apm_cpsr;           -- EXSTG store old cpsr
end record;

Type apc_dmstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_dmstg is record
  dummy : std_logic;
end record;

Enum lmd_memsize defined in /tmp/build_html/vhdl/libs/memdef.vhd

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

Type gdcl_param defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

Type apc_mestg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_mestg is record
  -- operation
  meop_enable : std_logic;
  meop_param  : gdcl_param;
  -- data
  mexc   : std_logic;
end record;

Constant APM_RREAL_U defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

constant APM_RREAL_U : integer := 4;

Constant APM_RREAL_D defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

constant APM_RREAL_D : integer := 0;

Enum slavestate defined in /tmp/build_html/vhdl/sparc/ahbtest.vhd

type slavestate is (idle, error, split, retry, ws1);

Enum dsnoop_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

type dsnoop_type is (none, slow, fast);

Enum apm_trap defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_trap is (
  apm_trap_reset,   -- reset
  apm_trap_undef,   -- undefined (EXSTG)
  apm_trap_swi,     -- software interrupt (DRSTG)
  apm_trap_prefch,  -- prefetch error (IMSTG)
  apm_trap_dabort,  -- data abort error (MESTG)
  apm_trap_irq,     -- interrupt
  apm_trap_fiq      -- fast interrupt
);

Type apm_trapctrl defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_trapctrl is record
  traptype : apm_trap;
  trap     : std_logic;
end record;

Type apc_wrstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_wrstg is record
  -- operation
  wrop_rd      : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  wrop_rdvalid : std_logic;
  wrop_setspsr : std_logic;
  wrop_trap    : apm_trapctrl;
end record;

Type apc_pctrl defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_pctrl is record
  insn : ade_insn;
  valid : std_logic;
  rr : apc_rrstg;
  rs : apc_rsstg;
  ex : apc_exstg;
  dm : apc_dmstg;
  me : apc_mestg;
  wr : apc_wrstg;
  data1 : std_logic_vector(31 downto 0);
  data2 : std_logic_vector(31 downto 0);
end record;

Type apc_pstate defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_pstate is record
  hold_r    : cli_hold;
  nextinsn_v : std_logic;
  dabort_v : std_logic;
  -- active cpsr
  fromEX_cpsr_r : apm_cpsr;
  -- pctrls of all stages from rrstg on 
  fromRR_pctrl_r : apc_pctrl;
  fromRS_pctrl_r : apc_pctrl;
  fromEX_pctrl_r : apc_pctrl;
  fromDM_pctrl_r : apc_pctrl;
  fromME_pctrl_r : apc_pctrl;
  fromWR_pctrl_r : apc_pctrl;
end record;

Type ade_feinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_feinsn is record
  insn    : std_logic_vector(31 downto 0);
  pc      : std_logic_vector(31 downto 0);
  pc_vir  : std_logic_vector(31 downto 0);
  valid   : std_logic;
  trap    : std_logic;
end record;

Type armiu_destg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_destg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   fromFE_insn_r : ade_feinsn;
   fromFE_insn_v : ade_feinsn;
end record;

Type ade_deinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_deinsn is record
  insn   : ade_insn;
  trap   : std_logic;
end record;

Type armiu_destg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_destg_typ_out is record
   toDR_insn_r : ade_deinsn;
   toDR_insn_v : ade_deinsn;
end record;

Type armiu_destg_tmp_type defined in /tmp/build_html/vhdl/arm/armiu_destg.vhd

type armiu_destg_tmp_type is record
    o : armiu_destg_typ_out;
    commit : std_logic;
    decinsn : ade_deinsn;
  end record;

Type armiu_destg_reg_type defined in /tmp/build_html/vhdl/arm/armiu_destg.vhd

type armiu_destg_reg_type is record
    decinsn : ade_deinsn;
    id      : std_logic_vector(2 downto 0);
  end record;

Type armiu_destg_dbg_type defined in /tmp/build_html/vhdl/arm/armiu_destg.vhd

type armiu_destg_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_destg_tmp_type;
     -- pragma translate_on
  end record;

Enum lmd_byteorder defined in /tmp/build_html/vhdl/libs/memdef.vhd

type lmd_byteorder is (lmd_big, lmd_little);

Function lmd_convert defined in /tmp/build_html/vhdl/libs/memdef.vhd

function lmd_convert (
  data : std_logic_vector(31 downto 0);
  intype : lmd_byteorder;
  outtype : lmd_byteorder
) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
begin
  tmp := data;
  if intype /= outtype then
    tmp := tmp(7 downto 0) & tmp(15 downto 8) & tmp(23 downto 16) & tmp(31 downto 24);
  end if;
  return tmp;
end;

Constant CFG_BO_INSN defined in /tmp/build_html/vhdl/config.vhd

constant CFG_BO_INSN : lmd_byteorder  := lmd_little;

Constant CFG_BO_PROC defined in /tmp/build_html/vhdl/config.vhd

constant CFG_BO_PROC : lmd_byteorder  := lmd_big;

Function ade_decode_v4 defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

function ade_decode_v4(
  insn_in : in std_logic_vector(31 downto 0)
) return ade_decinsn is
  variable arm_nop	 : std_logic;
  variable arm_mrs	 : std_logic;
  variable arm_bx	 : std_logic;
  variable arm_mul	 : std_logic;
  variable arm_mla	 : std_logic;
  variable arm_swp	 : std_logic;
  variable arm_sumull	 : std_logic;
  variable arm_sumlal	 : std_logic;
  variable arm_strhb	 : std_logic;
  variable arm_ldrhb	 : std_logic;
  variable arm_and	 : std_logic;
  variable arm_sub	 : std_logic;
  variable arm_eor	 : std_logic;
  variable arm_rsb	 : std_logic;
  variable arm_add	 : std_logic;
  variable arm_sbc	 : std_logic;
  variable arm_adc	 : std_logic;
  variable arm_rsc	 : std_logic;
  variable arm_msr	 : std_logic;
  variable arm_teq	 : std_logic;
  variable arm_cmn	 : std_logic;
  variable arm_tst	 : std_logic;
  variable arm_cmp	 : std_logic;
  variable arm_orr	 : std_logic;
  variable arm_bic	 : std_logic;
  variable arm_mov	 : std_logic;
  variable arm_mvn	 : std_logic;
  variable arm_str1	 : std_logic;
  variable arm_str2	 : std_logic;
  variable arm_str3	 : std_logic;
  variable arm_ldr1	 : std_logic;
  variable arm_undefined	 : std_logic;
  variable arm_stm	 : std_logic;
  variable arm_ldm	 : std_logic;
  variable arm_b	 : std_logic;
  variable arm_swi	 : std_logic;
  variable arm_cdp	 : std_logic;
  variable arm_mrc	 : std_logic;
  variable arm_mcr	 : std_logic;
  variable arm_stc	 : std_logic;
  variable arm_ldc	 : std_logic;
  variable vec_1	: std_logic_vector(1 downto 0);
  variable vec_2	: std_logic_vector(2 downto 0);
  variable vec_3	: std_logic_vector(4 downto 0);
  variable vec_4	: std_logic_vector(21 downto 0);
  variable vec_5	: std_logic_vector(12 downto 0);
  variable vec_6	: std_logic_vector(18 downto 0);
  variable vec_7	: std_logic_vector(4 downto 0);
  variable vec_8	: std_logic_vector(0 downto 0);
  variable vec_9	: std_logic_vector(0 downto 0);
  variable vec_10	: std_logic_vector(4 downto 0);
  variable vec_11	: std_logic_vector(0 downto 0);
  variable vec_12	: std_logic_vector(2 downto 0);
  variable vec_13	: std_logic_vector(0 downto 0);
  variable vec_14	: std_logic_vector(0 downto 0);
  variable vec_15	: std_logic_vector(0 downto 0);
  variable vec_16	: std_logic_vector(0 downto 0);
  variable vec_17	: std_logic_vector(6 downto 0);
  variable vec_18	: std_logic_vector(0 downto 0);
  variable vec_19	: std_logic_vector(0 downto 0);
  variable vec_20	: std_logic_vector(0 downto 0);
  variable vec_21	: std_logic_vector(0 downto 0);
  variable vec_22	: std_logic_vector(0 downto 0);
  variable vec_23	: std_logic_vector(0 downto 0);
  variable vec_24	: std_logic_vector(7 downto 0);
  variable vec_25	: std_logic_vector(0 downto 0);
  variable vec_26	: std_logic_vector(1 downto 0);
  variable vec_27	: std_logic_vector(0 downto 0);
  variable vec_28	: std_logic_vector(0 downto 0);
  variable vec_29	: std_logic_vector(0 downto 0);
  variable vec_30	: std_logic_vector(0 downto 0);
  variable vec_31	: std_logic_vector(0 downto 0);
  variable vec_32	: std_logic_vector(0 downto 0);
  variable vec_33	: std_logic_vector(0 downto 0);
  variable insn_return : ade_decinsn;
  variable insn : std_logic_vector(31 downto 0);
begin
  insn := insn_in;
  -- decoder assumes littleendian: word[3 2 1 0]
  insn := insn_in;
  if CFG_BO_PROC = lmd_big then
    insn := insn(7 downto 0) & insn(15 downto 8) & insn(23 downto 16) & insn(31 downto 24);
  end if;
  insn_return := type_arm_invalid;
  vec_1	 := insn(3 downto 2);
  vec_2	 := insn(31 downto 31)&insn(28 downto 28)&insn(1 downto 1);
  vec_3	 := insn(30 downto 29)&insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
  vec_4	 := insn(27 downto 16)&insn(14 downto 14)&insn(12 downto 4);
  arm_nop	 := '0';
  vec_5	 := insn(27 downto 24)&insn(19 downto 16)&insn(12 downto 8);
  arm_mrs	 := '0';
  vec_6	 := insn(30 downto 29)&insn(23 downto 8)&insn(0 downto 0);
  arm_bx	 := '0';
  vec_7	 := insn(30 downto 29)&insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
  vec_8	 := insn(14 downto 14);
  arm_mul	 := '0';
  vec_9	 := insn(14 downto 14);
  arm_mla	 := '0';
  vec_10	 := insn(19 downto 16)&insn(12 downto 12);
  arm_swp	 := '0';
  arm_sumull	 := '0';
  arm_sumlal	 := '0';
  vec_11	 := insn(12 downto 12);
  arm_strhb	 := '0';
  arm_ldrhb	 := '0';
  vec_12	 := insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
  vec_13	 := insn(14 downto 14);
  arm_and	 := '0';
  arm_sub	 := '0';
  vec_14	 := insn(14 downto 14);
  arm_eor	 := '0';
  arm_rsb	 := '0';
  vec_15	 := insn(14 downto 14);
  arm_add	 := '0';
  arm_sbc	 := '0';
  vec_16	 := insn(14 downto 14);
  arm_adc	 := '0';
  arm_rsc	 := '0';
  vec_17	 := insn(23 downto 20)&insn(12 downto 12)&insn(10 downto 9);
  arm_msr	 := '0';
  vec_18	 := insn(14 downto 14);
  arm_teq	 := '0';
  arm_cmn	 := '0';
  vec_19	 := insn(14 downto 14);
  arm_tst	 := '0';
  arm_cmp	 := '0';
  vec_20	 := insn(14 downto 14);
  arm_orr	 := '0';
  arm_bic	 := '0';
  vec_21	 := insn(14 downto 14);
  arm_mov	 := '0';
  arm_mvn	 := '0';
  vec_22	 := insn(12 downto 12);
  vec_23	 := insn(1 downto 1);
  arm_str1	 := '0';
  vec_24	 := insn(31 downto 28)&insn(19 downto 16);
  arm_str2	 := '0';
  vec_25	 := insn(28 downto 28);
  arm_str3	 := '0';
  arm_ldr1	 := '0';
  vec_26	 := insn(28 downto 28)&insn(1 downto 1);
  arm_undefined	 := '0';
  vec_27	 := insn(1 downto 1);
  vec_28	 := insn(12 downto 12);
  arm_stm	 := '0';
  arm_ldm	 := '0';
  arm_b	 := '0';
  vec_29	 := insn(1 downto 1);
  vec_30	 := insn(0 downto 0);
  arm_swi	 := '0';
  vec_31	 := insn(28 downto 28);
  arm_cdp	 := '0';
  vec_32	 := insn(12 downto 12);
  arm_mrc	 := '0';
  arm_mcr	 := '0';
  vec_33	 := insn(12 downto 12);
  arm_stc	 := '0';
  arm_ldc	 := '0';
case vec_1 is
  when "00" =>
    case vec_2 is
      when "000" =>
        case vec_3 is
          when "00111" =>
            case vec_4 is
              when "0000000000000000001110" =>
                arm_nop := '1';
                if arm_nop = '1' then
                insn_return := type_arm_nop;
                end if;
              when others => null;
            end case;
          when "00001" =>
            case vec_5 is
              when "0000000001111" =>
                arm_mrs := '1';
                if arm_mrs = '1' then
                insn_return := type_arm_mrs;
                end if;
              when others => null;
            end case;
          when others => null;
        end case;
      when "010" =>
        case vec_6 is
          when "0011111111001011111" =>
            arm_bx := '1';
            if arm_bx = '1' then
            insn_return := type_arm_bx;
            end if;
          when others => null;
        end case;
      when "110" =>
        case vec_7 is
          when "00000" =>
            case vec_8 is
              when "0" =>
                arm_mul := '1';
                if arm_mul = '1' then
                insn_return := type_arm_mul;
                end if;
              when others => null;
            end case;
          when "00010" =>
            case vec_9 is
              when "0" =>
                arm_mla := '1';
                if arm_mla = '1' then
                insn_return := type_arm_mla;
                end if;
              when others => null;
            end case;
          when "00001" =>
            case vec_10 is
              when "00000" =>
                arm_swp := '1';
                if arm_swp = '1' then
                insn_return := type_arm_swp;
                end if;
              when others => null;
            end case;
          when "00100" =>
            arm_sumull := '1';
            if arm_sumull = '1' then
            insn_return := type_arm_sumull;
            end if;
          when "00110" =>
            arm_sumlal := '1';
            if arm_sumlal = '1' then
            insn_return := type_arm_sumlal;
            end if;
          when others => null;
        end case;
        case vec_11 is
          when "0" =>
            arm_strhb := '1' and not (arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal);
            if arm_strhb = '1' then
            insn_return := type_arm_strhb;
            end if;
          when "1" =>
            arm_ldrhb := '1' and not (arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal);
            if arm_ldrhb = '1' then
            insn_return := type_arm_ldrhb;
            end if;
          when others => null;
        end case;
      when others => null;
    end case;
    case vec_12 is
      when "000" =>
        case vec_13 is
          when "0" =>
            arm_and := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_and = '1' then
            insn_return := type_arm_and;
            end if;
          when "1" =>
            arm_sub := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_sub = '1' then
            insn_return := type_arm_sub;
            end if;
          when others => null;
        end case;
      when "010" =>
        case vec_14 is
          when "0" =>
            arm_eor := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_eor = '1' then
            insn_return := type_arm_eor;
            end if;
          when "1" =>
            arm_rsb := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_rsb = '1' then
            insn_return := type_arm_rsb;
            end if;
          when others => null;
        end case;
      when "100" =>
        case vec_15 is
          when "0" =>
            arm_add := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_add = '1' then
            insn_return := type_arm_add;
            end if;
          when "1" =>
            arm_sbc := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_sbc = '1' then
            insn_return := type_arm_sbc;
            end if;
          when others => null;
        end case;
      when "110" =>
        case vec_16 is
          when "0" =>
            arm_adc := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_adc = '1' then
            insn_return := type_arm_adc;
            end if;
          when "1" =>
            arm_rsc := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_rsc = '1' then
            insn_return := type_arm_rsc;
            end if;
          when others => null;
        end case;
      when "011" =>
        case vec_17 is
          when "1111000" =>
            arm_msr := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_msr = '1' then
            insn_return := type_arm_msr;
            end if;
          when others => null;
        end case;
        case vec_18 is
          when "0" =>
            arm_teq := '1' and not (arm_msr or arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_teq = '1' then
            insn_return := type_arm_teq;
            end if;
          when "1" =>
            arm_cmn := '1' and not (arm_msr or arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_cmn = '1' then
            insn_return := type_arm_cmn;
            end if;
          when others => null;
        end case;
      when "001" =>
        case vec_19 is
          when "0" =>
            arm_tst := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_tst = '1' then
            insn_return := type_arm_tst;
            end if;
          when "1" =>
            arm_cmp := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_cmp = '1' then
            insn_return := type_arm_cmp;
            end if;
          when others => null;
        end case;
      when "101" =>
        case vec_20 is
          when "0" =>
            arm_orr := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_orr = '1' then
            insn_return := type_arm_orr;
            end if;
          when "1" =>
            arm_bic := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_bic = '1' then
            insn_return := type_arm_bic;
            end if;
          when others => null;
        end case;
      when "111" =>
        case vec_21 is
          when "0" =>
            arm_mov := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_mov = '1' then
            insn_return := type_arm_mov;
            end if;
          when "1" =>
            arm_mvn := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_mvn = '1' then
            insn_return := type_arm_mvn;
            end if;
          when others => null;
        end case;
      when others => null;
    end case;
  when "01" =>
    case vec_22 is
      when "0" =>
        case vec_23 is
          when "0" =>
            arm_str1 := '1';
            if arm_str1 = '1' then
            insn_return := type_arm_str1;
            end if;
          when "1" =>
            case vec_24 is
              when "00000000" =>
                arm_str2 := '1';
                if arm_str2 = '1' then
                insn_return := type_arm_str2;
                end if;
              when others => null;
            end case;
          when others => null;
        end case;
        case vec_25 is
          when "0" =>
            arm_str3 := '1' and not (arm_str1 or arm_str2);
            if arm_str3 = '1' then
            insn_return := type_arm_str3;
            end if;
          when others => null;
        end case;
      when "1" =>
        arm_ldr1 := '1';
        if arm_ldr1 = '1' then
        insn_return := type_arm_ldr1;
        end if;
      when others => null;
    end case;
    case vec_26 is
      when "11" =>
        arm_undefined := '1' and not (arm_str1 or arm_str2 or arm_str3 or arm_ldr1);
        if arm_undefined = '1' then
        insn_return := type_arm_undefined;
        end if;
      when others => null;
    end case;
  when "10" =>
    case vec_27 is
      when "0" =>
        case vec_28 is
          when "0" =>
            arm_stm := '1';
            if arm_stm = '1' then
            insn_return := type_arm_stm;
            end if;
          when "1" =>
            arm_ldm := '1';
            if arm_ldm = '1' then
            insn_return := type_arm_ldm;
            end if;
          when others => null;
        end case;
      when "1" =>
        arm_b := '1';
        if arm_b = '1' then
        insn_return := type_arm_b;
        end if;
      when others => null;
    end case;
  when "11" =>
    case vec_29 is
      when "1" =>
        case vec_30 is
          when "1" =>
            arm_swi := '1';
            if arm_swi = '1' then
            insn_return := type_arm_swi;
            end if;
          when "0" =>
            case vec_31 is
              when "0" =>
                arm_cdp := '1';
                if arm_cdp = '1' then
                insn_return := type_arm_cdp;
                end if;
              when "1" =>
                case vec_32 is
                  when "1" =>
                    arm_mrc := '1';
                    if arm_mrc = '1' then
                    insn_return := type_arm_mrc;
                    end if;
                  when "0" =>
                    arm_mcr := '1';
                    if arm_mcr = '1' then
                    insn_return := type_arm_mcr;
                    end if;
                  when others => null;
                end case;
              when others => null;
            end case;
          when others => null;
        end case;
      when "0" =>
        case vec_33 is
          when "0" =>
            arm_stc := '1';
            if arm_stc = '1' then
            insn_return := type_arm_stc;
            end if;
          when "1" =>
            arm_ldc := '1';
            if arm_ldc = '1' then
            insn_return := type_arm_ldc;
            end if;
          when others => null;
        end case;
      when others => null;
    end case;
  when others => null;
end case;
return insn_return;
end;

Constant ADE_COND_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_U  : integer := 31;

Constant ADE_COND_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_D  : integer := 28;

Constant ADE_COND_EQ defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_EQ : std_logic_vector(3 downto 0) := "0000";

Constant ADE_COND_NE defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_NE : std_logic_vector(3 downto 0) := "0001";

Constant ADE_COND_CS defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_CS : std_logic_vector(3 downto 0) := "0010";

Constant ADE_COND_CC defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_CC : std_logic_vector(3 downto 0) := "0011";

Constant ADE_COND_MI defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_MI : std_logic_vector(3 downto 0) := "0100";

Constant ADE_COND_PL defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_PL : std_logic_vector(3 downto 0) := "0101";

Constant ADE_COND_VS defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_VS : std_logic_vector(3 downto 0) := "0110";

Constant ADE_COND_VC defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_VC : std_logic_vector(3 downto 0) := "0111";

Constant ADE_COND_HI defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_HI : std_logic_vector(3 downto 0) := "1000";

Constant ADE_COND_LS defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_LS : std_logic_vector(3 downto 0) := "1001";

Constant ADE_COND_GE defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_GE : std_logic_vector(3 downto 0) := "1010";

Constant ADE_COND_LT defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_LT : std_logic_vector(3 downto 0) := "1011";

Constant ADE_COND_GT defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_GT : std_logic_vector(3 downto 0) := "1100";

Constant ADE_COND_LE defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_LE : std_logic_vector(3 downto 0) := "1101";

Constant ADE_COND_AL defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_AL : std_logic_vector(3 downto 0) := "1110";

Constant ADE_COND_NV defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_COND_NV : std_logic_vector(3 downto 0) := "1111";

Constant ADE_OP_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_U : integer := 24;

Constant ADE_OP_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_D : integer := 21;

Constant ADE_OP_AND defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_AND : std_logic_vector(3 downto 0) := "0000";

Constant ADE_OP_EOR defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_EOR : std_logic_vector(3 downto 0) := "0001";

Constant ADE_OP_SUB defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_SUB : std_logic_vector(3 downto 0) := "0010";

Constant ADE_OP_RSB defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_RSB : std_logic_vector(3 downto 0) := "0011";

Constant ADE_OP_ADD defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_ADD : std_logic_vector(3 downto 0) := "0100";

Constant ADE_OP_ADC defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_ADC : std_logic_vector(3 downto 0) := "0101";

Constant ADE_OP_SBC defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_SBC : std_logic_vector(3 downto 0) := "0110";

Constant ADE_OP_RSC defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_RSC : std_logic_vector(3 downto 0) := "0111";

Constant ADE_OP_TST defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_TST : std_logic_vector(3 downto 0) := "1000";

Constant ADE_OP_TEQ defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_TEQ : std_logic_vector(3 downto 0) := "1001";

Constant ADE_OP_CMP defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_CMP : std_logic_vector(3 downto 0) := "1010";

Constant ADE_OP_CMN defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_CMN : std_logic_vector(3 downto 0) := "1011";

Constant ADE_OP_ORR defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_ORR : std_logic_vector(3 downto 0) := "1100";

Constant ADE_OP_MOV defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_MOV : std_logic_vector(3 downto 0) := "1101";

Constant ADE_OP_BIC defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_BIC : std_logic_vector(3 downto 0) := "1110";

Constant ADE_OP_MVN defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_OP_MVN : std_logic_vector(3 downto 0) := "1111";

Constant ADE_SETCPSR_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_SETCPSR_C : integer := 20;

Constant ADE_MSR_R defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_MSR_R : integer := 22;

Constant ADE_MRS_R defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_MRS_R : integer := 22;

Constant ADE_MSR_IMM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_MSR_IMM : integer := 16;

Constant ADE_WB_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_WB_C : integer := 21;

Constant ADE_LDSTAMxLSV4AM_WB defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAMxLSV4AM_WB  : integer := 21;

Constant ADE_SWPB_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_SWPB_C : integer := 22;

Constant ADE_BROFF_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_BROFF_U : integer := 23;

Constant ADE_BROFF_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_BROFF_D : integer := 0;

Constant ADE_BRLINK_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_BRLINK_C : integer := 22;

Constant ADE_LDSTAM_OFF_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAM_OFF_U : integer := 11;

Constant ADE_LDSTAM_OFF_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAM_OFF_D : integer := 0;

Constant ADE_LSV4AM_OFF8_HU defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_OFF8_HU : integer := 11;

Constant ADE_LSV4AM_OFF8_HD defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_OFF8_HD : integer := 8;

Constant ADE_LSV4AM_OFF8_LU defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_OFF8_LU : integer := 3;

Constant ADE_LSV4AM_OFF8_LD defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_OFF8_LD : integer := 0;

Constant ADE_LDSTAM_UBYTE defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAM_UBYTE  : integer := 22;

Constant ADE_LSV4AM_SIGNED defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_SIGNED  : integer := 6;

Constant ADE_LSV4AM_HALF defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_HALF    : integer := 5;

Constant ADE_LDSTAMxLSV4AM_ADD defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAMxLSV4AM_ADD    : integer := 23;

Constant ADE_PAB_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_PAB_U : integer := 24;

Constant ADE_UID_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_UID_U : integer := 23;

Constant ADE_REGLIST_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_REGLIST_U  : integer := 15;

Constant ADE_REGLIST_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_REGLIST_D  : integer := 0;

Constant ADE_MRC_MCR_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_MRC_MCR_C : integer := 20;

Constant ADE_LDC_STC_WB_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDC_STC_WB_C : integer := 21;

Constant ADE_LDC_STC_P_C defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDC_STC_P_C : integer := 24;

Constant ADE_LDSTAMxLSV4AM_POS defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAMxLSV4AM_POS : integer := 24;

Constant ADE_RN_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_RN_U : integer := 19;

Constant ADE_RN_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_RN_D : integer := 16;

Constant ADE_RD_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_RD_U : integer := 15;

Constant ADE_RD_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_RD_D : integer := 12;

Constant ADE_RM_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_RM_U : integer := 3;

Constant ADE_RM_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_RM_D : integer := 0;

Constant ADE_SREG_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_SREG_U : integer := 11;

Constant ADE_SREG_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_SREG_D : integer := 8;

Function genmux defined in /tmp/build_html/vhdl/sparc/macro.vhd

function genmux(s,v : std_logic_vector) return std_logic is
variable res : std_logic_vector(v'length-1 downto 0); --'
variable i : integer;
begin
  res := v;
-- pragma translate_off
  i := 0;
  if not is_x(s) then
-- pragma translate_on
    i := conv_integer(unsigned(s));
-- pragma translate_off
  else
    res := (others => 'X');
  end if;
-- pragma translate_on
  return(res(i));
end;

Function xorv defined in /tmp/build_html/vhdl/sparc/macro.vhd

function xorv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
  tmp := '0';
  for i in d'range loop tmp := tmp xor d(i); end loop; --'
  return(tmp);
end;

Function orv defined in /tmp/build_html/vhdl/sparc/macro.vhd

function orv(d : std_logic_vector) return std_logic is
variable tmp : std_logic;
begin
  tmp := '0';
  for i in d'range loop tmp := tmp or d(i); end loop; --'
  return(tmp);
end;

Constant s012 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s012 : std_logic_vector(2 downto 0) := "000";

Constant s021 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s021 : std_logic_vector(2 downto 0) := "001";

Constant s102 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s102 : std_logic_vector(2 downto 0) := "010";

Constant s120 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s120 : std_logic_vector(2 downto 0) := "011";

Constant s201 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s201 : std_logic_vector(2 downto 0) := "100";

Constant s210 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s210 : std_logic_vector(2 downto 0) := "101";

Constant s0123 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s0123 : std_logic_vector(4 downto 0) := "00000";

Constant s0132 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s0132 : std_logic_vector(4 downto 0) := "00001";

Constant s0213 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s0213 : std_logic_vector(4 downto 0) := "00010";

Constant s0231 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s0231 : std_logic_vector(4 downto 0) := "00011";

Constant s0312 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s0312 : std_logic_vector(4 downto 0) := "00100";

Constant s0321 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s0321 : std_logic_vector(4 downto 0) := "00101";

Constant s1023 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s1023 : std_logic_vector(4 downto 0) := "00110";

Constant s1032 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s1032 : std_logic_vector(4 downto 0) := "00111";

Constant s1203 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s1203 : std_logic_vector(4 downto 0) := "01000";

Constant s1230 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s1230 : std_logic_vector(4 downto 0) := "01001";

Constant s1302 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s1302 : std_logic_vector(4 downto 0) := "01010";

Constant s1320 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s1320 : std_logic_vector(4 downto 0) := "01011";

Constant s2013 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s2013 : std_logic_vector(4 downto 0) := "01100";

Constant s2031 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s2031 : std_logic_vector(4 downto 0) := "01101";

Constant s2103 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s2103 : std_logic_vector(4 downto 0) := "01110";

Constant s2130 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s2130 : std_logic_vector(4 downto 0) := "01111";

Constant s2301 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s2301 : std_logic_vector(4 downto 0) := "10000";

Constant s2310 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s2310 : std_logic_vector(4 downto 0) := "10001";

Constant s3012 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s3012 : std_logic_vector(4 downto 0) := "10010";

Constant s3021 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s3021 : std_logic_vector(4 downto 0) := "10011";

Constant s3102 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s3102 : std_logic_vector(4 downto 0) := "10100";

Constant s3120 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s3120 : std_logic_vector(4 downto 0) := "10101";

Constant s3201 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s3201 : std_logic_vector(4 downto 0) := "10110";

Constant s3210 defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant s3210 : std_logic_vector(4 downto 0) := "10111";

Constant lru_3set_table defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant lru_3set_table : lru_3set_table_type :=
  ( (s120, s021, s012),                   -- s012
    (s210, s021, s012),                   -- s021
    (s120, s021, s102),                   -- s102
    (s120, s201, s102),                   -- s120
    (s210, s201, s012),                   -- s201
    (s210, s201, s102),                   -- s210
    (s210, s201, s102),                   -- dummy
    (s210, s201, s102)                    -- dummy
  );

Constant lru_4set_table defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant lru_4set_table : lru_4set_table_type :=
  ( (s1230, s0231, s0132, s0123),       -- s0123
    (s1320, s0321, s0132, s0123),       -- s0132
    (s2130, s0231, s0132, s0213),       -- s0213
    (s2310, s0231, s0312, s0213),       -- s0231
    (s3120, s0321, s0312, s0123),       -- s0312    
    (s3210, s0321, s0312, s0213),       -- s0321
    (s1230, s0231, s1032, s1023),       -- s1023
    (s1320, s0321, s1032, s1023),       -- s1032
    (s1230, s2031, s1032, s1203),       -- s1203
    (s1230, s2301, s1302, s1203),       -- s1230
    (s1320, s3021, s1302, s1023),       -- s1302
    (s1320, s3201, s1302, s1203),       -- s1320
    (s2130, s2031, s0132, s2013),       -- s2013
    (s2310, s2031, s0312, s2013),       -- s2031
    (s2130, s2031, s1032, s2103),       -- s2103
    (s2130, s2301, s1302, s2103),       -- s2130      
    (s2310, s2301, s3012, s2013),       -- s2301
    (s2310, s2301, s3102, s2103),       -- s2310
    (s3120, s3021, s3012, s0123),       -- s3012
    (s3210, s3021, s3012, s0213),       -- s3021
    (s3120, s3021, s3102, s1023),       -- s3102
    (s3120, s3201, s3102, s1203),       -- s3120
    (s3210, s3201, s3012, s2013),       -- s3201
    (s3210, s3201, s3102, s2103),       -- s3210
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103)         -- dummy
  );

Constant lru3_repl_table defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant lru3_repl_table : lru3_repl_table_type :=
  ( (0, 1, 2),      -- s012
    (0, 2, 2),      -- s021
    (1, 1, 2),      -- s102
    (1, 1, 2),      -- s120
    (2, 2, 2),      -- s201
    (2, 2, 2),      -- s210
    (2, 2, 2),      -- dummy
    (2, 2, 2)       -- dummy
  );

Constant lru4_repl_table defined in /tmp/build_html/vhdl/mem/cache/libs/setrepl_lib.vhd

constant lru4_repl_table : lru4_repl_table_type :=
  ( (0, 1, 2, 3), -- s0123
    (0, 1, 3, 3), -- s0132
    (0, 2, 2, 3), -- s0213
    (0, 2, 2, 3), -- s0231
    (0, 3, 3, 3), -- s0312
    (0, 3, 3, 3), -- s0321
    (1, 1, 2, 3), -- s1023
    (1, 1, 3, 3), -- s1032
    (1, 1, 2, 3), -- s1203
    (1, 1, 2, 3), -- s1230
    (1, 1, 3, 3), -- s1302
    (1, 1, 3, 3), -- s1320
    (2, 2, 2, 3), -- s2013
    (2, 2, 2, 3), -- s2031
    (2, 2, 2, 3), -- s2103
    (2, 2, 2, 3), -- s2130
    (2, 2, 2, 3), -- s2301
    (2, 2, 2, 3), -- s2310
    (3, 3, 3, 3), -- s3012
    (3, 3, 3, 3), -- s3021
    (3, 3, 3, 3), -- s3102
    (3, 3, 3, 3), -- s3120
    (3, 3, 3, 3), -- s3201
    (3, 3, 3, 3), -- s3210
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0)  -- dummy
  );

Constant PROC_CACHE_MAX defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

constant PROC_CACHE_MAX	: integer := 4;

Constant PROC_CACHETABLE defined in /tmp/build_html/vhdl/sparc/leon_config.vhd

constant PROC_CACHETABLE   : proc_cache_config_vector(0 to PROC_CACHE_MAX-1) := cachetbl_std;

Constant lastaddr defined in /tmp/build_html/vhdl/mem/cache/libs/kecs_libicache.vhd

constant lastaddr : std_logic_vector(KCML_IC_TLINE_BSZ-1 downto 0) := (others=>

Function is_cacheable defined in /tmp/build_html/vhdl/sparc/macro.vhd

function is_cacheable(haddr : std_logic_vector(31 downto 24)) return std_logic is
variable hcache : std_logic;
begin
--  hcache := '0';
--  for i in PROC_CACHETABLE'range loop	--'
--    if (haddr(31 downto 32-PROC_CACHE_ADDR_MSB) >= PROC_CACHETABLE(i).firstaddr) and
--      (haddr(31 downto 32-PROC_CACHE_ADDR_MSB) < PROC_CACHETABLE(i).lastaddr) 
--    then hcache := '1';  end if;
--  end loop;
--  return(hcache);

  if (haddr(31) = '0') and (haddr(30 downto 29) /= "01") then hcache := '1';
  else hcache := '0'; end if;
  return(hcache);
end;

Function decode defined in /tmp/build_html/vhdl/sparc/macro.vhd

function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_logic;
function xorv(d : std_logic_vector) return std_logic;
function orv(d : std_logic_vector) return std_logic;

-- 3-way set permutations
-- s012 => set 0 - least recently used
--         set 2 - most recently used
constant s012 : std_logic_vector(2 downto 0) := "000";
constant s021 : std_logic_vector(2 downto 0) := "001";
constant s102 : std_logic_vector(2 downto 0) := "010";
constant s120 : std_logic_vector(2 downto 0) := "011";
constant s201 : std_logic_vector(2 downto 0) := "100";
constant s210 : std_logic_vector(2 downto 0) := "101";


-- 4-way set permutations
-- s0123 => set 0 - least recently used
--          set 3 - most recently used
constant s0123 : std_logic_vector(4 downto 0) := "00000";
constant s0132 : std_logic_vector(4 downto 0) := "00001";
constant s0213 : std_logic_vector(4 downto 0) := "00010";
constant s0231 : std_logic_vector(4 downto 0) := "00011";
constant s0312 : std_logic_vector(4 downto 0) := "00100";
constant s0321 : std_logic_vector(4 downto 0) := "00101";
constant s1023 : std_logic_vector(4 downto 0) := "00110";
constant s1032 : std_logic_vector(4 downto 0) := "00111";
constant s1203 : std_logic_vector(4 downto 0) := "01000";
constant s1230 : std_logic_vector(4 downto 0) := "01001";
constant s1302 : std_logic_vector(4 downto 0) := "01010";
constant s1320 : std_logic_vector(4 downto 0) := "01011";
constant s2013 : std_logic_vector(4 downto 0) := "01100";
constant s2031 : std_logic_vector(4 downto 0) := "01101";
constant s2103 : std_logic_vector(4 downto 0) := "01110";
constant s2130 : std_logic_vector(4 downto 0) := "01111";
constant s2301 : std_logic_vector(4 downto 0) := "10000";
constant s2310 : std_logic_vector(4 downto 0) := "10001";
constant s3012 : std_logic_vector(4 downto 0) := "10010";
constant s3021 : std_logic_vector(4 downto 0) := "10011";
constant s3102 : std_logic_vector(4 downto 0) := "10100";
constant s3120 : std_logic_vector(4 downto 0) := "10101";
constant s3201 : std_logic_vector(4 downto 0) := "10110";
constant s3210 : std_logic_vector(4 downto 0) := "10111";

type lru_3set_table_vector_type is array(0 to 2) of std_logic_vector(2 downto 0);
type lru_3set_table_type is array (0 to 7) of lru_3set_table_vector_type;

constant lru_3set_table : lru_3set_table_type :=
  ( (s120, s021, s012),                   -- s012
    (s210, s021, s012),                   -- s021
    (s120, s021, s102),                   -- s102
    (s120, s201, s102),                   -- s120
    (s210, s201, s012),                   -- s201
    (s210, s201, s102),                   -- s210
    (s210, s201, s102),                   -- dummy
    (s210, s201, s102)                    -- dummy
  );
  
type lru_4set_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_4set_table_type is array(0 to 31) of lru_4set_table_vector_type;

constant lru_4set_table : lru_4set_table_type :=
  ( (s1230, s0231, s0132, s0123),       -- s0123
    (s1320, s0321, s0132, s0123),       -- s0132
    (s2130, s0231, s0132, s0213),       -- s0213
    (s2310, s0231, s0312, s0213),       -- s0231
    (s3120, s0321, s0312, s0123),       -- s0312    
    (s3210, s0321, s0312, s0213),       -- s0321
    (s1230, s0231, s1032, s1023),       -- s1023
    (s1320, s0321, s1032, s1023),       -- s1032
    (s1230, s2031, s1032, s1203),       -- s1203
    (s1230, s2301, s1302, s1203),       -- s1230
    (s1320, s3021, s1302, s1023),       -- s1302
    (s1320, s3201, s1302, s1203),       -- s1320
    (s2130, s2031, s0132, s2013),       -- s2013
    (s2310, s2031, s0312, s2013),       -- s2031
    (s2130, s2031, s1032, s2103),       -- s2103
    (s2130, s2301, s1302, s2103),       -- s2130      
    (s2310, s2301, s3012, s2013),       -- s2301
    (s2310, s2301, s3102, s2103),       -- s2310
    (s3120, s3021, s3012, s0123),       -- s3012
    (s3210, s3021, s3012, s0213),       -- s3021
    (s3120, s3021, s3102, s1023),       -- s3102
    (s3120, s3201, s3102, s1203),       -- s3120
    (s3210, s3201, s3012, s2013),       -- s3201
    (s3210, s3201, s3102, s2103),       -- s3210
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103),        -- dummy
    (s3210, s3201, s3102, s2103)         -- dummy
  );

type lru3_repl_table_single_type is array(0 to 2) of integer range 0 to 2;
type lru3_repl_table_type is array(0 to 7) of lru3_repl_table_single_type;

constant lru3_repl_table : lru3_repl_table_type :=
  ( (0, 1, 2),      -- s012
    (0, 2, 2),      -- s021
    (1, 1, 2),      -- s102
    (1, 1, 2),      -- s120
    (2, 2, 2),      -- s201
    (2, 2, 2),      -- s210
    (2, 2, 2),      -- dummy
    (2, 2, 2)       -- dummy
  );

type lru4_repl_table_single_type is array(0 to 3) of integer range 0 to 3;
type lru4_repl_table_type is array(0 to 31) of lru4_repl_table_single_type;

constant lru4_repl_table : lru4_repl_table_type :=
  ( (0, 1, 2, 3), -- s0123
    (0, 1, 3, 3), -- s0132
    (0, 2, 2, 3), -- s0213
    (0, 2, 2, 3), -- s0231
    (0, 3, 3, 3), -- s0312
    (0, 3, 3, 3), -- s0321
    (1, 1, 2, 3), -- s1023
    (1, 1, 3, 3), -- s1032
    (1, 1, 2, 3), -- s1203
    (1, 1, 2, 3), -- s1230
    (1, 1, 3, 3), -- s1302
    (1, 1, 3, 3), -- s1320
    (2, 2, 2, 3), -- s2013
    (2, 2, 2, 3), -- s2031
    (2, 2, 2, 3), -- s2103
    (2, 2, 2, 3), -- s2130
    (2, 2, 2, 3), -- s2301
    (2, 2, 2, 3), -- s2310
    (3, 3, 3, 3), -- s3012
    (3, 3, 3, 3), -- s3021
    (3, 3, 3, 3), -- s3102
    (3, 3, 3, 3), -- s3120
    (3, 3, 3, 3), -- s3201
    (3, 3, 3, 3), -- s3210
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0), -- dummy
    (0, 0, 0, 0)  -- dummy
  );

function is_cacheable(haddr : std_logic_vector(31 downto 24)) return std_logic;

end;

package body macro is

-- generic decoder

function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
  res := (others => '0');
-- pragma translate_off
  i := 0;
  if not is_x(v) then
-- pragma translate_on
    i := conv_integer(unsigned(v));
    res(i) := '1';
-- pragma translate_off
  else
    res := (others => 'X');
  end if;
-- pragma translate_on
  return(res);
end;

Constant ADE_DAPRAM_TYP defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAM_TYP   : integer := 25;

Constant ADE_DAPRAM_TYP_P defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAM_TYP_P : integer := 4;

Constant ADE_LDSTAM_TYP defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LDSTAM_TYP   : integer := 25;

Constant ADE_LSV4AM_TYP defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_LSV4AM_TYP   : integer := 22;

Constant ADE_DAPRAMxLDSTAM_SDIR_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAMxLDSTAM_SDIR_U     : integer := 6;

Constant ADE_DAPRAMxLDSTAM_SDIR_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAMxLDSTAM_SDIR_D     : integer := 5;

Constant ADE_DAPRAMxLDSTAM_SDIRNONE_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAMxLDSTAM_SDIRNONE_U : integer := 11;

Constant ADE_DAPRAMxLDSTAM_SDIRNONE_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAMxLDSTAM_SDIRNONE_D : integer := 4;

Constant ADE_DAPRAMxLDSTAM_SDIRROR_U defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAMxLDSTAM_SDIRROR_U  : integer := 11;

Constant ADE_DAPRAMxLDSTAM_SDIRROR_D defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

constant ADE_DAPRAMxLDSTAM_SDIRROR_D  : integer := 7;

Procedure ade_decode_amode defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

procedure ade_decode_amode (
  insn : in std_logic_vector(31 downto 0);
  am   : out ade_amode
);

-------------------------------------------------------------------------------

-- Implemented instructions:
type ade_decinsn is (
  type_arm_invalid,type_arm_nop,    type_arm_mrs,    type_arm_bx,    type_arm_mul,   type_arm_mla,
  type_arm_swp,    type_arm_sumull, type_arm_sumlal, type_arm_strhb, type_arm_ldrhb, type_arm_and,
  type_arm_sub,    type_arm_eor,    type_arm_rsb,    type_arm_add,   type_arm_sbc,   type_arm_adc, 
  type_arm_msr,    type_arm_teq,    type_arm_cmn,    type_arm_tst,   type_arm_cmp,   type_arm_orr, 
  type_arm_mov,    type_arm_mvn,    type_arm_str1,   type_arm_str2,  type_arm_str3,  type_arm_ldr1,
  type_arm_stm,    type_arm_ldm,    type_arm_b,      type_arm_swi,   type_arm_cdp,   type_arm_mrc,
  type_arm_mcr,    type_arm_stc,    type_arm_ldc,    type_arm_rsc,   type_arm_bic,   type_arm_undefined
);

-- Instruction groups
type ade_insntyp is (
  ade_typmem,
  ade_typalu,
  ade_typmisc,
  ade_typcp
);

-- this decoder is automatically generated by "decgen"
function ade_decode_v4(
  insn_in : in std_logic_vector(31 downto 0)
) return ade_decinsn;

-------------------------------------------------------------------------------
-- Condition code

constant ADE_COND_U  : integer := 31;
constant ADE_COND_D  : integer := 28;
constant ADE_COND_EQ : std_logic_vector(3 downto 0) := "0000";
constant ADE_COND_NE : std_logic_vector(3 downto 0) := "0001";
constant ADE_COND_CS : std_logic_vector(3 downto 0) := "0010";
constant ADE_COND_CC : std_logic_vector(3 downto 0) := "0011";
constant ADE_COND_MI : std_logic_vector(3 downto 0) := "0100";
constant ADE_COND_PL : std_logic_vector(3 downto 0) := "0101";
constant ADE_COND_VS : std_logic_vector(3 downto 0) := "0110";
constant ADE_COND_VC : std_logic_vector(3 downto 0) := "0111";
constant ADE_COND_HI : std_logic_vector(3 downto 0) := "1000";
constant ADE_COND_LS : std_logic_vector(3 downto 0) := "1001";
constant ADE_COND_GE : std_logic_vector(3 downto 0) := "1010";
constant ADE_COND_LT : std_logic_vector(3 downto 0) := "1011";
constant ADE_COND_GT : std_logic_vector(3 downto 0) := "1100";
constant ADE_COND_LE : std_logic_vector(3 downto 0) := "1101";
constant ADE_COND_AL : std_logic_vector(3 downto 0) := "1110";
constant ADE_COND_NV : std_logic_vector(3 downto 0) := "1111";

-------------------------------------------------------------------------------
-- Alu codes

constant ADE_OP_U : integer := 24;
constant ADE_OP_D : integer := 21;
constant ADE_OP_AND : std_logic_vector(3 downto 0) := "0000";
constant ADE_OP_EOR : std_logic_vector(3 downto 0) := "0001";
constant ADE_OP_SUB : std_logic_vector(3 downto 0) := "0010";
constant ADE_OP_RSB : std_logic_vector(3 downto 0) := "0011";
constant ADE_OP_ADD : std_logic_vector(3 downto 0) := "0100";
constant ADE_OP_ADC : std_logic_vector(3 downto 0) := "0101";
constant ADE_OP_SBC : std_logic_vector(3 downto 0) := "0110";
constant ADE_OP_RSC : std_logic_vector(3 downto 0) := "0111";
constant ADE_OP_TST : std_logic_vector(3 downto 0) := "1000";
constant ADE_OP_TEQ : std_logic_vector(3 downto 0) := "1001";
constant ADE_OP_CMP : std_logic_vector(3 downto 0) := "1010";
constant ADE_OP_CMN : std_logic_vector(3 downto 0) := "1011";
constant ADE_OP_ORR : std_logic_vector(3 downto 0) := "1100";
constant ADE_OP_MOV : std_logic_vector(3 downto 0) := "1101";
constant ADE_OP_BIC : std_logic_vector(3 downto 0) := "1110";
constant ADE_OP_MVN : std_logic_vector(3 downto 0) := "1111";

constant ADE_SETCPSR_C : integer := 20;  -- set cpsr

-------------------------------------------------------------------------------
-- swp, msr, mrs codes

constant ADE_MSR_R : integer := 22;  -- '1' = spsr: '0' = cpsr
constant ADE_MRS_R : integer := 22;  -- '1' = spsr: '0' = cpsr
constant ADE_MSR_IMM : integer := 16;   -- '1' = imm; '0' = reg

constant ADE_WB_C : integer := 21;      -- same as ADE_LDSTAMxLSV4AM_WB
constant ADE_SWPB_C : integer := 22;    -- 1=SWPB,0=SWP

constant ADE_BROFF_U : integer := 23;     -- branch offset
constant ADE_BROFF_D : integer := 0;
constant ADE_BRLINK_C : integer := 22;

-------------------------------------------------------------------------------
-- ld, st codes

constant ADE_LDSTAM_OFF_U : integer := 11;  -- <offset12> of armcmd_l1.vhd LDSSTAM
constant ADE_LDSTAM_OFF_D : integer := 0;

constant ADE_LSV4AM_OFF8_HU : integer := 11;  -- <offset8> of armcmd_l4.vhd LSV4AM
constant ADE_LSV4AM_OFF8_HD : integer := 8;
constant ADE_LSV4AM_OFF8_LU : integer := 3;
constant ADE_LSV4AM_OFF8_LD : integer := 0;

constant ADE_LDSTAM_UBYTE  : integer := 22;  -- '1': unsigned byte, '0': word
constant ADE_LSV4AM_SIGNED  : integer := 6;  -- '1': unsigned byte, '0': word
constant ADE_LSV4AM_HALF    : integer := 5;  -- '1': unsigned byte, '0': word
constant ADE_LDSTAMxLSV4AM_ADD    : integer := 23;  -- '1': add, '0': sub

constant ADE_PAB_U : integer := 24;     -- '0': after / '1': before
constant ADE_UID_U : integer := 23;     -- '1':increment / '0':decrement

constant ADE_REGLIST_U  : integer := 15;
constant ADE_REGLIST_D  : integer := 0;

-------------------------------------------------------------------------------
-- coprocessor

constant ADE_MRC_MCR_C : integer := 20;  -- '1':MRC '0':MCR
constant ADE_LDC_STC_WB_C : integer := 21;  -- '1': writeback '0': nowriteback (ADE_LDSTAMxLSV4AM_WB)
constant ADE_LDC_STC_P_C : integer := 24;  -- '1': Post; '0': Pre (negate ADE_LDSTAMxLSV4AM_POS)

-------------------------------------------------------------------------------
-- registers

constant ADE_RN_U : integer := 19;
constant ADE_RN_D : integer := 16;
constant ADE_RD_U : integer := 15;
constant ADE_RD_D : integer := 12;
constant ADE_RM_U : integer := 3;
constant ADE_RM_D : integer := 0;
constant ADE_SREG_U : integer := 11;  -- shieft register
constant ADE_SREG_D : integer := 8;

-------------------------------------------------------------------------------

-- festg out insn
type ade_feinsn is record
  insn    : std_logic_vector(31 downto 0);
  pc      : std_logic_vector(31 downto 0);
  pc_vir  : std_logic_vector(31 downto 0);
  valid   : std_logic;
  trap    : std_logic;
end record;

-- Decoded insn
type ade_insn is record
  pc_8    : std_logic_vector(31 downto 0);
  insn    : std_logic_vector(31 downto 0);
  insntyp : ade_insntyp;
  decinsn : ade_decinsn;
  am      : ade_amode;
  valid   : std_logic;
  id      : std_logic_vector(2 downto 0);
end record;

-- destg out insn
type ade_deinsn is record
  insn   : ade_insn;
  trap   : std_logic;
end record;

-------------------------------------------------------------------------------

end armdecode;

package body armdecode is

-- Addressing mode decode constants
-- DAPRAM: am.DAPRAM_typ 
constant ADE_DAPRAM_TYP   : integer := 25; -- '1': imm rot, '0': sreg/simm (shiefted)
constant ADE_DAPRAM_TYP_P : integer := 4;  -- shiefted: ('0': imm , '1': reg)
-- LDSTAM: am.LDSTAM_typ
constant ADE_LDSTAM_TYP   : integer := 25; -- '0': adm_LDSTAM_imm, '1': adm_LDSTAM_reg (shiefted)
-- LSV4AM: am.LSV4AM_typ
constant ADE_LSV4AM_TYP   : integer := 22; -- '1': adm_LSV4AM_imm , '0': adm_LSV4AM_reg
-- DAPRAM, LDSTAM: am.DAPRAMxLDSTAM_sdir
constant ADE_DAPRAMxLDSTAM_SDIR_U     : integer := 6;  -- shieft type 
constant ADE_DAPRAMxLDSTAM_SDIR_D     : integer := 5;
constant ADE_DAPRAMxLDSTAM_SDIRNONE_U : integer := 11; -- no shieft
constant ADE_DAPRAMxLDSTAM_SDIRNONE_D : integer := 4;
constant ADE_DAPRAMxLDSTAM_SDIRROR_U  : integer := 11; -- ror 
constant ADE_DAPRAMxLDSTAM_SDIRROR_D  : integer := 7;   
-- LDSTAM, LSV4AM: am.LDSTAMxLSV4AM_pos
-- LDSTAM, LSV4AM: am.LDSTAMxLSV4AM_wb
-- LDSTAM, LSV4AM: am.LDSTAMxLSV4AM_uacc
constant ADE_LDSTAMxLSV4AM_POS : integer := 24; -- '0': postindexed, '1': preindexed
constant ADE_LDSTAMxLSV4AM_WB  : integer := 21; -- postindexed: 0 = normal, 1 = usermode
  
procedure ade_decode_amode (
  insn : in std_logic_vector(31 downto 0);
  am   : out ade_amode
) is
  variable tmp : std_logic_vector(4 downto 0);
begin

  -- DAPRAM: typ
  am.DAPRAM_typ := ade_DAPRAM_simm;
  if insn(ADE_DAPRAM_TYP_P) = '1' then
    am.DAPRAM_typ := ade_DAPRAM_sreg;
  end if;
  
  -- DPAM and LSAM: shieft direction
  am.DAPRAMxLDSTAM_sdir := ash_sdir_srrx;
  case insn(ADE_DAPRAMxLDSTAM_SDIR_U downto ADE_DAPRAMxLDSTAM_SDIR_D) is
    when "00" =>
      am.DAPRAMxLDSTAM_sdir := ash_sdir_slsl;
      if insn(ADE_DAPRAMxLDSTAM_SDIRNONE_U downto ADE_DAPRAMxLDSTAM_SDIRNONE_D) = "00000000" then
        am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
      end if;
    when "01" => am.DAPRAMxLDSTAM_sdir := ash_sdir_slsr;
    when "10" => am.DAPRAMxLDSTAM_sdir := ash_sdir_sasr;
    when "11" =>
      if not (insn(ADE_DAPRAMxLDSTAM_SDIRROR_U downto ADE_DAPRAMxLDSTAM_SDIRROR_D) = "00000") then
        am.DAPRAMxLDSTAM_sdir := ash_sdir_sror;
      end if;
    when others => null;
  end case;
  
  -- DAPRAM: typ
  if insn(ADE_DAPRAM_TYP) = '1' then
    am.DAPRAM_typ := ade_DAPRAM_immrot;
  end if;
  
  -- LDSTAM: typ
  am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
  if insn(ADE_LDSTAM_TYP) = '1' then
    am.LDSTAM_typ := ade_LDSTAMxLSV4AM_reg;
    -- am.DAPRAMxLDSTAM_sdir := ade_snone;
  end if;
  
  -- LDSTAM and LSV4AM: preindexed / postindexed
  am.LDSTAMxLSV4AM_uacc := '0';
  am.LDSTAMxLSV4AM_wb := '1';
  if insn(ADE_LDSTAMxLSV4AM_POS) = '1' then
    am.LDSTAMxLSV4AM_pos := ade_pre; 
    if insn(ADE_LDSTAMxLSV4AM_WB) = '0' then
      am.LDSTAMxLSV4AM_wb := '0';
    end if;
  else
    am.LDSTAMxLSV4AM_pos := ade_post;
    if insn(ADE_LDSTAMxLSV4AM_WB) = '1' then
      am.LDSTAMxLSV4AM_uacc := '1';
    end if;
  end if;
  
  -- LSV4AM: offset, register (not shiefted)
  am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
  if insn(ADE_LSV4AM_TYP) = '0' then
    am.LSV4AM_typ := ade_LDSTAMxLSV4AM_reg;
  end if;

end;

Enum states defined in /tmp/build_html/vhdl/sparc/mmutw.vhd

type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);

Function lin_convint defined in /tmp/build_html/vhdl/libs/int.vhd

function lin_convint (
  op   : in std_logic_vector
) return integer is
variable tmp : integer;
begin
  tmp := 0;
-- pragma translate_off
    if not (is_x(op)) then
-- pragma translate_on
      tmp := conv_integer(op);
-- pragma translate_off
    end if;
-- pragma translate_on
  return tmp;
end;

Function lin_decode defined in /tmp/build_html/vhdl/libs/int.vhd

function lin_decode(
  v : std_logic_vector
) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0); --'
variable i : natural;
begin
  res := (others => '0');
-- pragma translate_off
  i := 0;
  if not is_x(v) then
-- pragma translate_on
    i := conv_integer(unsigned(v));
    res(i) := '1';
-- pragma translate_off
  else
    res := (others => 'X');
  end if;
-- pragma translate_on
  return(res);
end;

Constant lin_log2x defined in /tmp/build_html/vhdl/libs/int.vhd

constant lin_log2x : lin_log2arr := (1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Function lin_countzero defined in /tmp/build_html/vhdl/libs/int.vhd

function lin_countzero(
  data : in    std_logic_vector
) return std_logic_vector is
variable z02 : std_logic_vector((data'length/2)-1 downto 0);
variable z04 : std_logic_vector((data'length/4)-1 downto 0);
variable d04 : std_logic_vector(3 downto 0);
variable z08 : std_logic_vector((data'length/8)-1 downto 0);
variable d08 : std_logic_vector(7 downto 0);
variable z16 : std_logic_vector((data'length/16)-1 downto 0);
variable d16 : std_logic_vector(15 downto 0);
variable z32 : std_logic_vector((data'length/32)-1 downto 0);
variable d32 : std_logic_vector(31 downto 0);
variable z64 : std_logic_vector((data'length/64)-1 downto 0);
variable d64 : std_logic_vector(63 downto 0);
variable res : std_logic_vector(lin_log2x(data'length)-1 downto 0);
variable length : integer;
variable tmp : integer;
begin

  res := (others => '0');
  z32 := (others => '0');
  z02 := (others => '0');
  z04 := (others => '0');
  length := data'length;
  
  if (length / 2) >= 1 then
    tmp := 0;
L02:
    for i in (length/2)-1 downto 0 loop
      tmp := i;
      if    (data((i*2)+0) = '1') then
        z02(i) := '1';
        exit L02;
      elsif (data((i*2)+1) = '1') then
        z02(i) := '0';
        exit L02;
      else
        z02(i) := '0';
      end if;
    end loop;  -- i
    if (length = 2) then
      res(0) := z02(tmp);
    end if;
  end if;
  
  if (length / 4) >= 1 then
    tmp := 0;
L04:
    for i in (length/4)-1 downto 0 loop
      tmp := i;
      d04 := data((i*4)+3 downto i*4);
      z04(i) := '1';
      if    not (d04(3 downto 2) = "00") then
        z04(i) := '1';
        res(0) := z02(i*2);
        exit L04;
      elsif not (d04(1 downto 0) = "00") then
        z04(i) := '0';
        res(0) := z02((i*2)+1);
        exit L04;
      else
        z04(i) := '0';
      end if;
    end loop;  -- i
    if (length = 4) then
      res(1) := z04(tmp);
    end if;
  end if;
  
  if (length / 8) >= 1 then
    tmp := 0;
L08:
    for i in (length/8)-1 downto 0 loop
      tmp := i;
      d08 := data((i*8)+7 downto i*8);
      z08(i) := '1';
      if    not (d08(7 downto 4) = "0000") then
        z08(i) := '1';
        res(1) := z04(i*2);
        exit L08;
      elsif not (d08(3 downto 0) = "0000") then
        z08(i) := '0';
        res(1) := z04((i*2)+1);
        exit L08;
      else
        z08(i) := '0';
      end if;
    end loop;  -- i
    if (length = 8) then
      res(2) := z08(tmp);
    end if;
  end if;
  
  if (length / 16) >= 1 then
    tmp := 0;
L16:
    for i in (length/16)-1 downto 0 loop
      tmp := i;
      d16 := data((i*16)+15 downto i*16);
      z16(i) := '1';
      if    not (d16(15 downto 8) = "00000000") then
        z16(i) := '1';
        res(2) := z08(i*2);
        exit L16;
      elsif not (d16(7 downto 0) = "00000000") then
        z16(i) := '0';
        res(2) := z08((i*2)+1);
        exit L16;
      else
        z16(i) := '0';
      end if;
    end loop;  -- i
    if (length = 16) then
      res(3) := z16(tmp);
    end if;
  end if;

  if (length / 32) >= 1 then
    tmp := 0;
L32:
    for i in (length/32)-1 downto 0 loop
      tmp := i;
      d32 := data((i*32)+31 downto i*32);
      z32(i) := '1';
      if    not (d32(31 downto 16) = "0000000000000000") then
        z32(i) := '1';
        res(3) := z16(i*2);
        exit L32;
      elsif not (d32(15 downto 0) = "0000000000000000") then
        z32(i) := '0';
        res(3) := z16((i*2)+1);
        exit L32;
      else
        z32(i) := '0';
      end if;
    end loop;  -- i
    if (length = 32) then
      res(4) := z32(tmp);
    end if;
  end if;
  
  if (length / 64) >= 1 then
    tmp := 0;
L64:
    for i in (length/64)-1 downto 0 loop
      tmp := i;
      d64 := data((i*64)+63 downto i*64);
      z64(i) := '1';
      if    not (d64(63 downto 32) = "00000000000000000000000000000000") then
        z64(i) := '1';
        res(4) := z32(i*2);
        exit L64;
      elsif not (d64(31 downto 0) = "00000000000000000000000000000000") then
        z64(i) := '0';
        res(4) := z32((i*2)+1);
        exit L64;
      else
        z64(i) := '0';
      end if;
    end loop;  -- i
    if (length = 64) then
      res(5) := z64(tmp);
    end if;
  end if;

  return res;
end;

Procedure lin_adder defined in /tmp/build_html/vhdl/libs/int.vhd

procedure lin_adder(
  op1   : in std_logic_vector(31 downto 0);
  op2   : in std_logic_vector(31 downto 0);
  carry : in std_logic;
  sub   : in std_logic;
  sum   : out std_logic_vector(31 downto 0)
) is
begin
-- pragma translate_off
    if not (is_x(op1) or is_x(op2) or is_x(carry)) then
-- pragma translate_on
      if sub = '1' then
        sum := op1 - op2 - carry;
      else
        sum := op1 + op2 + carry;
      end if;
-- pragma translate_off
    else
      sum := (others => 'X');
    end if;
-- pragma translate_on

end;

Constant log2 defined in /tmp/build_html/vhdl/sparc/leon_config.vhd

constant log2  : log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Constant lin_log2 defined in /tmp/build_html/vhdl/libs/int.vhd

constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Procedure lin_incdec defined in /tmp/build_html/vhdl/libs/int.vhd

procedure lin_incdec(
  source : in    std_logic_vector;
  dest   : inout std_logic_vector;
  do     : in    std_logic;
  inc    : in    std_logic
);
  
-- convert std_logic_vector to integer
function lin_convint(
  op   : in std_logic_vector
) return integer;

-- set bit integer(v)
function lin_decode(
  v : std_logic_vector
) return std_logic_vector;

-- pos of first '1' from left
function lin_countzero(
  data : in    std_logic_vector
) return std_logic_vector;

-- adder with carryin
procedure lin_adder(
  op1   : in std_logic_vector(31 downto 0);
  op2   : in std_logic_vector(31 downto 0);
  carry : in std_logic;
  sub   : in std_logic;
  sum   : out std_logic_vector(31 downto 0)
);

----------------------------------------------------------------------------
-- log2 tables
----------------------------------------------------------------------------

type lin_log2arr is array(1 to 64) of integer;
constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others => 6);
constant lin_log2x : lin_log2arr := (1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others => 6);

end int;

package body int is
  
procedure lin_incdec(
  source : in    std_logic_vector;
  dest   : inout std_logic_vector;
  do     : in    std_logic;
  inc    : in    std_logic
) is
variable tmp : std_logic_vector(source'range);
begin

  tmp := (others => '0');
-- pragma translate_off
    if not is_x(source) then
-- pragma translate_on
      if inc = '1' then
        tmp := source(source'range) + 1;
      else
        tmp := source(source'range) - 1;
      end if;
-- pragma translate_off
    else
      tmp := (others => 'X');
    end if;
-- pragma translate_on

    if (do) = '1' then
      dest := tmp;
    end if;

end;

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution