/tmp/build_html/vhdl/arm/armcache.vhd : l8arm - synthesizable ARM v4 vhdl model.

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-- $(lic)
-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use work.amba.all;
use work.bus_comp.all;
use work.corelib.all;
use work.cache_comp.all;
use work.genic_lib.all;
use work.gendc_lib.all;
use work.cache_comp.all;
use work.bus_comp.all;

entity armcache is
  port ( 
    rst    : in  std_logic;
    clk    : in  std_logic;
    hold   : in cli_hold;
    ici    : in genic_type_in;
    ico    : out genic_type_out;
    dci    : in gendc_type_in;
    dco    : out gendc_type_out;
    ahbi   : in  ahb_mst_in_type;
    ahbo   : out ahb_mst_out_type;
    apbi   : in  apb_slv_in_type;
    apbo   : out apb_slv_out_type
    );
end armcache;

architecture rtl of armcache is

  type armcache_tmp_type is record
    dummy      : std_logic;
  end record;
  type armcache_reg_type is record
    genic_ctrl : gicl_ctrl;
    gendc_ctrl : gdcl_ctrl;
  end record;
  type armcache_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armcache_tmp_type;
     -- pragma translate_on
  end record;
  signal r, c       : armcache_reg_type;
  signal rdbg, cdbg : armcache_dbg_type;

  signal mi : ahbmst_mp_in_a(1 downto 0);
  signal mo : ahbmst_mp_out_a(1 downto 0);
  
  signal genic_i    : genic_type_in;
  signal genic_o    : genic_type_out;
  signal genic_ctrl : gicl_ctrl;
  signal genic_icmo : gencmem_type_ic_out;
  signal genic_icmi : gencmem_type_ic_in;
  signal genic_mcio : ahbmst_mp_out;
  signal genic_mcii : ahbmst_mp_in;
  
  signal gendc_i    : gendc_type_in;
  signal gendc_o    : gendc_type_out;
  signal gendc_ctrl : gdcl_ctrl;
  signal gendc_dcmo : gencmem_type_dc_out;
  signal gendc_dcmi : gencmem_type_dc_in;
  signal gendc_wbi  : genwb_type_in;
  signal gendc_wbo  : genwb_type_out;
  
  signal genwb_i     : genwb_type_in;
  signal genwb_o     : genwb_type_out;
  signal genwb_mcwbo : ahbmst_mp_out;
  signal genwb_mcwbi : ahbmst_mp_in;

  signal gencmem_i  : gencmem_type_in;
  signal gencmem_o  : gencmem_type_out;
  
begin  
    
  p0: process (clk, rst, r, apbi )
    variable v    : armcache_reg_type;
    variable t    : armcache_tmp_type;
    variable vdbg : armcache_dbg_type;
  begin 
    
    -- $(init(t:armcache_tmp_type))
    
    v := r;
    
    -- reset
    if ( rst = '0' ) then
      v.genic_ctrl.burst := '0';
      v.gendc_ctrl.writeback := '0';
      v.gendc_ctrl.allocateonstore := '0';
    end if;
    
    c <= v;
    
    genic_ctrl <= r.genic_ctrl;
    gendc_ctrl <= r.gendc_ctrl;
    
    -- pragma translate_off
    vdbg := rdbg;
    vdbg.dbg := t;
    cdbg <= vdbg;
    -- pragma translate_on  
    
  end process p0;
    
  pregs : process (clk, c)
  begin
    if rising_edge(clk) then
      r <= c;
      -- pragma translate_off
      rdbg <= cdbg;
      -- pragma translate_on
    end if;
  end process;


  ic0: genic port map ( rst, clk, hold, genic_i, genic_o, genic_ctrl, genic_icmo, genic_icmi,
                        genic_mcio, genic_mcii );
  genic_i <= ici;
  ico <= genic_o;
  genic_mcio <= mo(0);
  mi(0) <= genic_mcii;

  dc0: gendc port map ( rst, clk, hold, gendc_i, gendc_o, gendc_ctrl, gendc_dcmo, gendc_dcmi,
                        gendc_wbi, gendc_wbo );
  gendc_i <= dci;
  dco <= gendc_o;
  
  wb0: genwb port map ( rst, clk, genwb_i, genwb_o, genwb_mcwbo, genwb_mcwbi );
  genwb_i <= gendc_wbi;
  gendc_wbo <= genwb_o;
  genwb_mcwbo <= mo(1);
  mi(1) <= genwb_mcwbi;

  cm0: gencmem port map ( rst, clk, gencmem_i, gencmem_o);
  gencmem_i.ic <= genic_icmi;
  genic_icmo <= gencmem_o.ic;
  gencmem_i.dc <= gendc_dcmi;
  gendc_dcmo <= gencmem_o.dc;
  
  ahbmast0: ahbmst_mp generic map ( AHBMST_PORTS => 2)
                      port map ( rst, clk, mi, mo, ahbi, ahbo );

end rtl;

File /tmp/build_html/vhdl/mem/cache/libs/genic_lib.vhd
used by /tmp/build_html/vhdl/mem/cache/cache_comp.vhd
used by /tmp/build_html/vhdl/mem/cache/gencmem.vhd
used by /tmp/build_html/vhdl/mem/cache/genic.vhd
used by /tmp/build_html/vhdl/mem/cache/gendc.vhd
used by /tmp/build_html/vhdl/arm/armcache.vhd
used by /tmp/build_html/vhdl/arm/tbench_armcache.vhd

File /tmp/build_html/vhdl/arm/armcache.vhd

Enum astates defined in /tmp/build_html/vhdl/sparc/mmu_acache.vhd

type astates is (idle, dcache, icache, mmu);

Enum rdatatype defined in /tmp/build_html/vhdl/sparc/mmu_icache.vhd

type rdatatype is (itag, idata, memory);

Type cli_hold defined in /tmp/build_html/vhdl/core/libs/corelib.vhd

type cli_hold is record
   hold : std_logic; -- hold
   dhold : std_logic; -- dcache hold
   ihold : std_logic; -- icache hold
end record;

Enum states defined in /tmp/build_html/vhdl/sparc/mmutw.vhd

type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);

Type genic_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genic_type_in is record
  pc_r : std_logic_vector(31 downto 0);
  pc_v : std_logic_vector(31 downto 0);
  bra_r : std_logic;
  bra_v : std_logic;
  annul : std_logic;
  flush : std_logic;
end record;

Enum txfsmtype defined in /tmp/build_html/vhdl/sparc/dcom_uart.vhd

type txfsmtype is (idle, data, stopbit);

Constant CFG_IC_DLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_IC_DLINE_SZ  : integer range 1 to 4  := 1;

Type gcml_ic_dline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

type gcml_ic_dline is record
  data : std_logic_vector_a(CFG_IC_DLINE_SZ-1 downto 0);
end record;

Type genic_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genic_type_out is record
  dat_line_v  : gcml_ic_dline;
  mstrobe : std_logic;
  hold : std_logic;
end record;

Enum cpins_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type cpins_type is (none, cpop, load, store);

Enum lmd_memsize defined in /tmp/build_html/vhdl/libs/memdef.vhd

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

Type gdcl_param defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

Type gendc_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gendc_type_in is record
  addr_in : std_logic_vector(31 downto 0);  -- incoming
  data_in : std_logic_vector(31 downto 0);
  addr_re : std_logic_vector(31 downto 0);  -- registered
  data_re : std_logic_vector(31 downto 0);
  addrin_re : std_logic;

  -- todo: locking on atomic load store does not work yet
  -- until no multiprocessor system is implemented it's defered to the future

  atomic_readwrite : std_logic;
  
  forcewrite : std_logic;
  forceread : std_logic;
  
  param_r : gdcl_param;
  annul : std_logic;
end record;

Type gendc_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gendc_type_out is record
  wr_data : std_logic_vector(31 downto 0);
  me_mexc : std_logic;
  wr_mexc : std_logic;
  hold : std_logic;
end record;

Type armcache_tmp_type defined in /tmp/build_html/vhdl/arm/armcache.vhd

type armcache_tmp_type is record
    dummy      : std_logic;
  end record;

Type gicl_ctrl defined in /tmp/build_html/vhdl/mem/cache/libs/genic_lib.vhd

type gicl_ctrl is record
  burst : std_logic;
end record;

Type gdcl_ctrl defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd

type gdcl_ctrl is record
  writeback : std_logic;
  allocateonstore : std_logic;
end record;

Type armcache_reg_type defined in /tmp/build_html/vhdl/arm/armcache.vhd

type armcache_reg_type is record
    genic_ctrl : gicl_ctrl;
    gendc_ctrl : gdcl_ctrl;
  end record;

Type armcache_dbg_type defined in /tmp/build_html/vhdl/arm/armcache.vhd

type armcache_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armcache_tmp_type;
     -- pragma translate_on
  end record;

Constant CFG_IC_SETS defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_IC_SETS     : integer range 1 to 4  := 1;

Type gencmem_type_ic_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gencmem_type_ic_out is record
  -- # read tag out
  tag_line  : gcml_ic_tline_a(CFG_IC_SETS-1 downto 0);
  -- # read data out
  dat_line  : gcml_ic_dline_a(CFG_IC_SETS-1 downto 0);
end record;

Constant CFG_IC_ADDR_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_IC_ADDR_SZ  : integer := 32;

Constant lin_log2 defined in /tmp/build_html/vhdl/libs/int.vhd

constant lin_log2  : lin_log2arr := (0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,
				5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,others =>

Constant CFG_IC_SET_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_IC_SET_SZ   : integer range 1 to 64 := 1;

Constant GCML_IC_TTAG_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

constant GCML_IC_TTAG_BSZ : integer := CFG_IC_ADDR_SZ - (2 + (8 +lin_log2(CFG_IC_SET_SZ)));

Constant CFG_IC_TLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_IC_TLINE_SZ  : integer range 2 to 8  := 4;

Type gcml_ic_tline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

type gcml_ic_tline is record
  tag   : std_logic_vector(GCML_IC_TTAG_BSZ-1 downto 0);
  valid : std_logic_vector(CFG_IC_TLINE_SZ-1 downto 0);
  lock : std_logic;
end record;

Type gencmem_type_ic_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gencmem_type_ic_in is record
  addr  : std_logic_vector(31 downto 0);
  -- # write tag in
  tag_line  : gcml_ic_tline;
  tag_write : std_logic_vector(CFG_IC_SETS-1 downto 0);
  -- # write data in
  dat_line  : gcml_ic_dline;
  dat_write : std_logic_vector(CFG_IC_SETS-1 downto 0);
end record;

Enum unit_status_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type unit_status_type is (free, started, ready);

Enum slavestate defined in /tmp/build_html/vhdl/sparc/ahbtest.vhd

type slavestate is (idle, error, split, retry, ws1);

Enum execstate defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type execstate is (nominal, excpend, exception);

File /tmp/build_html/vhdl/sparc/cache.vhd

Type ahbmst_mp_out defined in /tmp/build_html/vhdl/bus/bus_comp.vhd

type ahbmst_mp_out is record
  data             : std_logic_vector(31 downto 0); -- memory data
  ready            : std_logic;			    -- cycle ready
  grant            : std_logic;			    -- 
  retry            : std_logic;			    -- 
  mexc             : std_logic;			    -- memory exception
  cache            : std_logic;		-- cacheable data
end record;

Enum ahbmst_state_type defined in /tmp/build_html/vhdl/sparc/pci_oc.vhd

type ahbmst_state_type is (idle, req, respond);

Type ahbmst_mp_in defined in /tmp/build_html/vhdl/bus/bus_comp.vhd

type ahbmst_mp_in is record
  req              : std_logic;
  address          : std_logic_vector(31 downto 0); 
  data             : std_logic_vector(31 downto 0);
  size             : lmd_memsize;
  burst            : std_logic;
  read             : std_logic;
  lock             : std_logic;
end record;

Constant CFG_DC_SETS defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_DC_SETS     : integer range 1 to 4  := 1;

Type gencmem_type_dc_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gencmem_type_dc_out is record
  -- # read tag out
  tag_line  : gcml_dc_tline_a(CFG_DC_SETS-1 downto 0);
  -- # read data out
  dat_line  : gcml_dc_dline_a(CFG_DC_SETS-1 downto 0);
end record;

Constant CFG_DC_ADDR_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_DC_ADDR_SZ  : integer := 32;

Constant CFG_DC_SET_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_DC_SET_SZ   : integer range 1 to 64 := 1;

Constant GCML_DC_TTAG_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

constant GCML_DC_TTAG_BSZ   : integer := CFG_DC_ADDR_SZ - (2 + (8 +lin_log2(CFG_DC_SET_SZ)));

Constant CFG_DC_TLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_DC_TLINE_SZ  : integer range 2 to 8  := 4;

Type gcml_dc_tline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

type gcml_dc_tline is record
  tag   : std_logic_vector(GCML_DC_TTAG_BSZ-1 downto 0);
  valid : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0);
  dirty : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0);
  lock : std_logic;
end record;

Constant CFG_DC_DLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_DC_DLINE_SZ  : integer range 1 to 8 := 1;

Constant GCML_DC_DADDR_BSZ defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

constant GCML_DC_DADDR_BSZ : integer := ((8 +lin_log2(CFG_DC_SET_SZ))-lin_log2(CFG_DC_DLINE_SZ));

Type gcml_dc_dline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

type gcml_dc_dline is record
  data : std_logic_vector_a(CFG_DC_DLINE_SZ-1 downto 0);
end record;

Type gencmem_type_dc_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gencmem_type_dc_in is record
  addr  : std_logic_vector(31 downto 0);
  -- # write tag in
  tag_line  : gcml_dc_tline;
  tag_write : std_logic_vector(CFG_DC_SETS-1 downto 0);
  -- # write data in
  --dat_addr  : std_logic_vector(GCML_DC_DADDR_BSZ-1 downto 0);
  dat_line  : gcml_dc_dline;
  dat_write : std_logic_vector(CFG_DC_SETS-1 downto 0);
end record;

Type gwbl_entry defined in /tmp/build_html/vhdl/mem/cache/libs/genwb_lib.vhd

type gwbl_entry is record
  addr : std_logic_vector(31 downto 0);
  data : std_logic_vector(31 downto 0);
  burst : std_logic;
  size : lmd_memsize;
  read : std_logic;
  lock : std_logic;                     -- lock until next req
end record;

Type genwb_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genwb_type_in is record
  fifo_write : std_logic;
  fifo_entry : gwbl_entry;
end record;

Type genwb_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genwb_type_out is record
  fifo_stored_v : std_logic;
  empty_v : std_logic;

  read_finish_v : std_logic;
  read_mexc : std_logic;
  read_data : std_logic_vector(31 downto 0);
end record;

Type gencmem_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gencmem_type_in is record
  ic : gencmem_type_ic_in;
  dc : gencmem_type_dc_in;
end record;

Type gencmem_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gencmem_type_out is record
  ic : gencmem_type_ic_out;
  dc : gencmem_type_dc_out;
end record;

File /tmp/build_html/vhdl/mem/cache/genic.vhd

File /tmp/build_html/vhdl/mem/cache/gendc.vhd

File /tmp/build_html/vhdl/mem/cache/genwb.vhd

File /tmp/build_html/vhdl/mem/cache/gencmem.vhd

File /tmp/build_html/vhdl/bus/ahbmst_mp.vhd

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution