/tmp/build_html/vhdl/arm/arm_comp.vhd : l8arm - synthesizable ARM v4 vhdl model.

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-- $(lic)
-- $(help_generic)
-- $(help_local)

library IEEE;
use IEEE.std_logic_1164.all;
use work.amba.all;
use work.corelib.all;
use work.bus_comp.all;
use work.cache_comp.all;
use work.ctrl_comp.all;
use work.armpctrl.all;
use work.armpmodel.all;
use work.armdecode.all;

package arm_comp is

type arm_proc_typ_in is record
   irqo : irq_iu_out_type;
end record;

type arm_proc_typ_out is record
   irqi : irq_iu_in_type;
end record;

component arm_proc
  generic (
    TEST_CACHE : boolean := false
  );
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    clkn   : in  std_logic;
    i      : in arm_proc_typ_in;
    o      : out arm_proc_typ_out;
    ahbi   : in  ahb_mst_in_type;
    ahbo   : out ahb_mst_out_type;
    apbi   : in  apb_slv_in_type;
    apbo   : out apb_slv_out_type
  );
end component; 

component armcache 
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    hold   : in cli_hold;
    ici    : in genic_type_in;
    ico    : out genic_type_out;
    dci    : in gendc_type_in;
    dco    : out gendc_type_out;
    ahbi   : in  ahb_mst_in_type;
    ahbo   : out ahb_mst_out_type;
    apbi   : in  apb_slv_in_type;
    apbo   : out apb_slv_out_type
  );
end component;  

type armiu_typ_in is record
   irqo : irq_iu_out_type;
end record;

type armiu_typ_out is record
   irqi : irq_iu_in_type;
end record;

component armiu 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    clkn    : in  std_logic;
    hold    : in cli_hold;
    ici     : out genic_type_in;
    ico     : in genic_type_out;
    dci     : out gendc_type_in;
    dco     : in gendc_type_out;
    i       : in  armiu_typ_in;
    o       : out armiu_typ_out
    );
end component;

component tbench_armcache 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    clkn    : in  std_logic;
    hold    : in cli_hold;
    ici     : out genic_type_in;
    ico     : in genic_type_out;
    dci     : out gendc_type_in;
    dco     : in gendc_type_out;
    i       : in  armiu_typ_in;
    o       : out armiu_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- imstg inputs:
-- pstate          : [rrstg,wrstg] pctrls + hold + nextinsn

type armiu_imstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   branch_v : std_logic;
   addrvir_v : std_logic_vector(31 downto 0);
end record;

-- imstg outputs:
-- toFE_addrphy_v   : translated physical address
-- toFE_addrvir_v   : current virtual address
-- toFE_addrvalid_v : addr valid ('0' after pflush until next branchaddr enters)
-- toFE_branch_v    : is branch
-- toFE_trap_v      : prefectch trap

type armiu_imstg_typ_out is record
   toFE_addrphy_v   : std_logic_vector(31 downto 0);
   toFE_addrvir_v   : std_logic_vector(31 downto 0);
   toFE_addrvalid_v : std_logic;
   toFE_branch_v    : std_logic;
   toFE_trap_v      : std_logic;
end record;

component armiu_imstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_imstg_typ_in;
    o       : out armiu_imstg_typ_out
    );
end component;

-------------------------------------------------------------------------------
-- festg inputs:
-- pstate          : [rrstg,wrstg] pctrls + hold + nextinsn
-- fromIM_addrphy_v   : translated physical address
-- fromIM_addrvir_v   : current virtual address
-- fromIM_addrvalid_v : addr valid ('0' after pflush until next branchaddr enters)
-- fromIM_branch_v    : is branch
-- fromIM_trap_v      : prefectch trap

type armiu_festg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   ico   : genic_type_out;
   fromIM_addrphy_v   : std_logic_vector(31 downto 0);
   fromIM_addrvir_v   : std_logic_vector(31 downto 0);
   fromIM_addrvalid_v : std_logic;
   fromIM_branch_v    : std_logic;
   fromIM_trap_v      : std_logic;
end record;

-- festg outputs:
-- toDE_insn_r    : fetched insn (drives destg)
-- toDE_insn_v    : next cycle fetched insn (sampled on pstate.hold and pstate.nextinsn)

type armiu_festg_typ_out is record
   ici   : genic_type_in;
   toDE_insn_r : ade_feinsn;
   toDE_insn_v : ade_feinsn;
end record;

component armiu_festg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_festg_typ_in;
    o       : out armiu_festg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- destg inputs:
-- pstate          : [rrstg,wrstg] pctrls + hold + nextinsn
-- fromFE_insn_r   : fetched insn (drives destg)
-- fromFE_insn_v   : next cycle fetched insn (sampled in festg on pstate.hold and pstate.nextinsn)

type armiu_destg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   fromFE_insn_r : ade_feinsn;
   fromFE_insn_v : ade_feinsn;
end record;

-- destg outputs:
-- toDR_insn_r    : decoded insn (drives drstg)
-- toDR_insn_v    : next cycle decoded insn, (sampled on pstate.hold and pstate.nextinsn)

type armiu_destg_typ_out is record
   toDR_insn_r : ade_deinsn;
   toDR_insn_v : ade_deinsn;
end record;

component armiu_destg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_destg_typ_in;
    o       : out armiu_destg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- drstg inputs:
-- fromDE_insn_r      : decoded insn (drives drstg)
-- fromDE_insn_v      : next cycle decoded insn, (sampled in destg on pstate.hold and pstate.nextinsn)
-- fromRR_nextmicro_v : register locking from rrstg
-- fromWR_dabort_v     : data abort in wrstg
-- fromCPDE_accept    : coprocessor accept cmd (for undef trap)
-- fromCPDE_busy      : coprocessor lock until ready
-- fromCPDE_last      : coprocessor (ldc,stc) last addr

type armiu_drstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromDE_insn_r : ade_deinsn;
   fromDE_insn_v : ade_deinsn;
   fromRR_nextmicro_v : std_logic;
   fromWR_dabort_v : std_logic;

   fromCPDE_accept : std_logic;
   fromCPDE_busy : std_logic;
   fromCPDE_last : std_logic;

end record;

-- drstg outputs:
-- toRR_micro_v    : pctrl + src regs assemble next microcode to rrstg
-- id              : cmd id
type armiu_drstg_typ_out is record
   nextinsn_v : std_logic;
   toRR_micro_v : apc_micro;
   id : std_logic_vector(2 downto 0);
end record;

component armiu_drstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_drstg_typ_in;
    o       : out armiu_drstg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- rrstg inputs:
-- pstate            : [rrstg,wrstg] pctrls + hold
-- fromDR_micro_v    : pctrl + src regs assemble by drstg
-- fromEX_alures_v   : current aluresult of exstg for forwarding 
-- fromWR_rd_v       : wrstg write: write reg
-- fromWR_rd_valid_v : wrstg write: write enable
-- fromWR_rd_data_v  : wrstg write: write data
-- fromCPEX_data     : coprocessor cpreg->armreg, cpreg->mem (mrc,stc)
-- fromCPEX_lock     : coprocessor holds pipeline

type armiu_rrstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromDR_micro_v : apc_micro;                           
   fromEX_alures_v : std_logic_vector(31 downto 0);
   
   fromWR_rd_v : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
   fromWR_rd_valid_v : std_logic;
   fromWR_rd_data_v : std_logic_vector(31 downto 0);
   
   fromCPEX_data : std_logic_vector(31 downto 0);
   fromCPEX_lock : std_logic;
end record;

-- rrstg outputs:
-- fromRR_nextmicro_v : register locking (also coprocessor registers)

type armiu_rrstg_typ_out is record
   pctrl_r : apc_pctrl;
   toRS_pctrl_v : apc_pctrl;
   
   toDR_nextmicro_v  : std_logic;
end record;

component armiu_rrstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    clkn    : in  std_logic;
    i       : in  armiu_rrstg_typ_in;
    o       : out armiu_rrstg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- rsstg inputs:
-- pstate          : [rrstg,wrstg] pctrls + hold
-- fromRR_pctrl_v  : next pctrl, sampled on pstate.hold = '0'
-- fromEX_alures_v : current aluresult of exstg for forwarding (rsop_op(1|2)_src = apc_opsrc_alures)
-- fromEX_cpsr_v   : exstg cpsr (carry for shiefter)

type armiu_rsstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromRR_pctrl_v : apc_pctrl;
   fromEX_alures_v : std_logic_vector(31 downto 0);
   fromEX_cpsr_v : apm_cpsr;
end record;

type armiu_rsstg_typ_out is record
   pctrl_r : apc_pctrl;
   toEX_pctrl_v : apc_pctrl;
end record;

component armiu_rsstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_rsstg_typ_in;
    o       : out armiu_rsstg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- exstg inputs:
-- pstate           : [rrstg,wrstg] pctrls + hold
-- fromRS_pctrl_v   : next pctrl, sampled on pstate.hold = '0'
-- fromWR_spsr_r    : wrstg spsr (for mrs,msr)
-- fromWR_cpsr_v    : wrstg write cpsr 
-- fromWR_cpsrset_v : wrstg write cpsr enable
-- fromCP_active    : coprocessor active (for undef trap)

type armiu_exstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromRS_pctrl_v : apc_pctrl;

   fromWR_spsr_r  : apm_spsr;
   fromWR_cpsr_v  : apm_cpsr;
   fromWR_cpsrset_v : std_logic;
  
   fromCP_active : std_logic;
end record;

-- exstg outputs:
-- cpsr_r   : exstg cpsr
-- cpsr_v   : exstg cpsr next cycle
-- alures_v : current aluresult
-- toIM_branch_v : alures_v into imstg as address
-- flush_v       : flush [imstg-rsstg]
type armiu_exstg_typ_out is record
   pctrl_r : apc_pctrl;
   toDM_pctrl_v : apc_pctrl;
   
   cpsr_r : apm_cpsr;
   cpsr_v : apm_cpsr;
   alures_v : std_logic_vector(31 downto 0);
   
   toIM_branch_v : std_logic;
   flush_v : std_logic;
   
end record;

component armiu_exstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_exstg_typ_in;
    o       : out armiu_exstg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- dmstg inputs:
-- pstate          : [rrstg,wrstg] pctrls + hold
-- fromEX_pctrl_v  : next pctrl, sampled on pstate.hold = '0'

type armiu_dmstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromEX_pctrl_v : apc_pctrl;
end record;

type armiu_dmstg_typ_out is record
   pctrl_r : apc_pctrl;
   toME_pctrl_v : apc_pctrl;
end record;

component armiu_dmstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_dmstg_typ_in;
    o       : out armiu_dmstg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- mestg inputs:
-- pstate          : [rrstg,wrstg] pctrls + hold
-- fromDM_pctrl_v  : next pctrl, sampled on pstate.hold = '0'
-- dci             : dcache input
-- irqo            : irq ctrl output

-- mestg outputs:

type armiu_mestg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   irqo : irq_iu_out_type;
   fromDM_pctrl_v : apc_pctrl;
end record;

type armiu_mestg_typ_out is record
   pctrl_r : apc_pctrl;
   toWR_pctrl_v : apc_pctrl;
   dci   : gendc_type_in;
end record;

component armiu_mestg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_mestg_typ_in;
    o       : out armiu_mestg_typ_out
    );
end component;

-------------------------------------------------------------------------------

-- wrstg inputs:
-- pstate            : [rrstg,wrstg] pctrls + hold
-- fromME_pctrl_v    : next pctrl, sampled on pstate.hold = '0'
-- dco               : dcache output
-- fromCP_data       : coprocessor armreg->cpreg (mcr)

type armiu_wrstg_typ_in is record
   pstate : apc_pstate;
   fromME_pctrl_v : apc_pctrl;
   dco   : gendc_type_out;
   
   fromCP_data : std_logic_vector(31 downto 0);
end record;

-- wrstg outputs:
-- spsr_r            : wrstg spsr;
-- toIM_branch_v     : branch on memload->pc or trap
-- toIM_branchaddr_v : branch addr
-- toDR_dabort_v     : signal dabort
-- toEX_cpsr_v       : set exstg cpsr
-- toEX_cpsrset_v    : set exstg cpsr enable
-- toRR_rd_v         : write rd reg
-- toRR_rd_valid_v   : write rd enable
-- toRR_rd_data_v    : write rd data
-- toCPWR_crd_data_v : coprocessor mem->cpreg data (ldc)
-- irqi              : irqctrl irq ack
type armiu_wrstg_typ_out is record
   pctrl_r : apc_pctrl;

   spsr_r : apm_spsr;

   irqi : irq_iu_in_type;
   
   toIM_branch_v : std_logic;
   toIM_branchaddr_v : std_logic_vector(31 downto 0);
   
   toDR_dabort_v : std_logic;

   toEX_cpsr_v : apm_cpsr;
   toEX_cpsrset_v : std_logic;

   toRR_rd_v : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
   toRR_rd_valid_v : std_logic;
   toRR_rd_data_v : std_logic_vector(31 downto 0);
   
   toCPWR_crd_data_v : std_logic_vector(31 downto 0);
end record;

component armiu_wrstg 
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    i       : in  armiu_wrstg_typ_in;
    o       : out armiu_wrstg_typ_out
    );
end component;

end arm_comp;

File /tmp/build_html/vhdl/core/ctrl/ctrl_comp.vhd
used by /tmp/build_html/vhdl/core/ctrl/irqctrl.vhd
used by /tmp/build_html/vhdl/core/ctrl/irqctrl2.vhd
used by /tmp/build_html/vhdl/core/ctrl/timers.vhd
used by /tmp/build_html/vhdl/arm/arm_comp.vhd
used by /tmp/build_html/vhdl/arm/armiu_mestg.vhd
used by /tmp/build_html/vhdl/core/soc_gen.vhd
used by /tmp/build_html/vhdl/core/core.vhd

Constant zero defined in /tmp/build_html/vhdl/sparc/pci_gr.vhd

constant zero : std_logic_vector(31 downto 0) := (others =>

Type irq_iu_out_type defined in /tmp/build_html/vhdl/core/ctrl/ctrl_comp.vhd

type irq_iu_out_type is record
  irl   	: std_logic_vector(3 downto 0);   -- zero = no irq
end record;

Type arm_proc_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type arm_proc_typ_in is record
   irqo : irq_iu_out_type;
end record;

Type irq_iu_in_type defined in /tmp/build_html/vhdl/core/ctrl/ctrl_comp.vhd

type irq_iu_in_type is record
  intack	: std_logic;                      -- interrupt acknoledge (clear i.irl bit)
  irl		: std_logic_vector(3 downto 0);   
end record;

Type arm_proc_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type arm_proc_typ_out is record
   irqi : irq_iu_in_type;
end record;

File /tmp/build_html/vhdl/arm/arm_proc.vhd

File /tmp/build_html/vhdl/arm/armcache.vhd

Enum astates defined in /tmp/build_html/vhdl/sparc/mmu_acache.vhd

type astates is (idle, dcache, icache, mmu);

Enum rdatatype defined in /tmp/build_html/vhdl/sparc/mmu_icache.vhd

type rdatatype is (itag, idata, memory);

Type cli_hold defined in /tmp/build_html/vhdl/core/libs/corelib.vhd

type cli_hold is record
   hold : std_logic; -- hold
   dhold : std_logic; -- dcache hold
   ihold : std_logic; -- icache hold
end record;

Enum states defined in /tmp/build_html/vhdl/sparc/mmutw.vhd

type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);

Type genic_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genic_type_in is record
  pc_r : std_logic_vector(31 downto 0);
  pc_v : std_logic_vector(31 downto 0);
  bra_r : std_logic;
  bra_v : std_logic;
  annul : std_logic;
  flush : std_logic;
end record;

Enum txfsmtype defined in /tmp/build_html/vhdl/sparc/dcom_uart.vhd

type txfsmtype is (idle, data, stopbit);

Constant CFG_IC_DLINE_SZ defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd

constant CFG_IC_DLINE_SZ  : integer range 1 to 4  := 1;

Type gcml_ic_dline defined in /tmp/build_html/vhdl/mem/cache/libs/gencmem_lib.vhd

type gcml_ic_dline is record
  data : std_logic_vector_a(CFG_IC_DLINE_SZ-1 downto 0);
end record;

Type genic_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type genic_type_out is record
  dat_line_v  : gcml_ic_dline;
  mstrobe : std_logic;
  hold : std_logic;
end record;

Enum cpins_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type cpins_type is (none, cpop, load, store);

Enum lmd_memsize defined in /tmp/build_html/vhdl/libs/memdef.vhd

type lmd_memsize is (
  lmd_word,
  lmd_byte,
  lmd_half,
  lmd_dbl
);

Type gdcl_param defined in /tmp/build_html/vhdl/mem/cache/libs/gendc_lib.vhd

type gdcl_param is record
  size      : lmd_memsize;
  read      : std_logic;
  lock      : std_logic;
  writedata : std_logic;
  addrin    : std_logic;
  signed    : std_logic;
end record;

Type gendc_type_in defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gendc_type_in is record
  addr_in : std_logic_vector(31 downto 0);  -- incoming
  data_in : std_logic_vector(31 downto 0);
  addr_re : std_logic_vector(31 downto 0);  -- registered
  data_re : std_logic_vector(31 downto 0);
  addrin_re : std_logic;

  -- todo: locking on atomic load store does not work yet
  -- until no multiprocessor system is implemented it's defered to the future

  atomic_readwrite : std_logic;
  
  forcewrite : std_logic;
  forceread : std_logic;
  
  param_r : gdcl_param;
  annul : std_logic;
end record;

Type gendc_type_out defined in /tmp/build_html/vhdl/mem/cache/cache_comp.vhd

type gendc_type_out is record
  wr_data : std_logic_vector(31 downto 0);
  me_mexc : std_logic;
  wr_mexc : std_logic;
  hold : std_logic;
end record;

Type armiu_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_typ_in is record
   irqo : irq_iu_out_type;
end record;

Type armiu_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_typ_out is record
   irqi : irq_iu_in_type;
end record;

File /tmp/build_html/vhdl/arm/armiu.vhd

File /tmp/build_html/vhdl/arm/tbench_armcache.vhd

Enum mcycletype defined in /tmp/build_html/vhdl/peripherals/mem/sdmctrl.vhd

type mcycletype is (midle, active, leadout);

Type apm_excpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_excpsr is record
   n      : std_logic;                  -- negative
   z      : std_logic;                  -- zero
   c      : std_logic;                  -- carry
   v      : std_logic;                  -- overflow
   -- extensions
   -- fext   : std_logic_vector(3 downto 0);  -- cpsr(27:24)
   -- xext   : std_logic_vector(7 downto 0);  -- cpsr(15:8)
   -- sext   : std_logic_vector(7 downto 0);  -- cpsr(23:16)
end record;

Type apm_wrcpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_wrcpsr is record
   i      : std_logic;                  -- [7] irq
   f      : std_logic;                  -- [6] fiq
   t      : std_logic;                  -- [5] thumb
   mode   : std_logic_vector(4 downto 0);
-- pragma translate_off
--   dbgmode  : aba_atyp_dbgpmode;       -- readable pmode for dbg
-- pragma translate_on
end record;

Type apm_cpsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_cpsr is record
   ex : apm_excpsr;
   wr : apm_wrcpsr;
end record;

Enum ade_insntyp defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_insntyp is (
  ade_typmem,
  ade_typalu,
  ade_typmisc,
  ade_typcp
);

Enum ade_decinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_decinsn is (
  type_arm_invalid,type_arm_nop,    type_arm_mrs,    type_arm_bx,    type_arm_mul,   type_arm_mla,
  type_arm_swp,    type_arm_sumull, type_arm_sumlal, type_arm_strhb, type_arm_ldrhb, type_arm_and,
  type_arm_sub,    type_arm_eor,    type_arm_rsb,    type_arm_add,   type_arm_sbc,   type_arm_adc, 
  type_arm_msr,    type_arm_teq,    type_arm_cmn,    type_arm_tst,   type_arm_cmp,   type_arm_orr, 
  type_arm_mov,    type_arm_mvn,    type_arm_str1,   type_arm_str2,  type_arm_str3,  type_arm_ldr1,
  type_arm_stm,    type_arm_ldm,    type_arm_b,      type_arm_swi,   type_arm_cdp,   type_arm_mrc,
  type_arm_mcr,    type_arm_stc,    type_arm_ldc,    type_arm_rsc,   type_arm_bic,   type_arm_undefined
);

Enum ade_DAPRAM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_DAPRAM is (
  ade_DAPRAM_simm,       -- OP2 shieft with imm 
  ade_DAPRAM_sreg,       -- OP2 shieft with reg 
  ade_DAPRAM_immrot      -- OP2 immidiate rotated
);

Enum ade_LDSTAMxLSV4AM defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_LDSTAMxLSV4AM is (
  ade_LDSTAMxLSV4AM_imm,  -- addr v1 imm
                          -- addr v4 imm
  ade_LDSTAMxLSV4AM_reg   -- addr v1 reg (shieft with imm)
                          -- addr v4 reg
);

Enum icycletype defined in /tmp/build_html/vhdl/peripherals/mem/sdmctrl.vhd

type icycletype is (iidle, pre, ref1, ref2, lmode, finish);

Enum ade_pos defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_pos is (
  ade_pre,      -- pre indexed
  ade_post      -- post indexed
);

Enum ash_sdir defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd

type ash_sdir is (
  ash_sdir_snone,    -- no shieft
  ash_sdir_slsl,     -- LSL #: logical shieft left 
  ash_sdir_slsr,     -- LSR #: logical shieft righ
  ash_sdir_sasr,     -- ASR #: arithmetic shieft left
  ash_sdir_sror,     -- ROR #: rotate 
  ash_sdir_srrx      -- RRX #: rotate 1 with carry
);

Type ade_amode defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_amode is record
  DAPRAM_typ           : ade_DAPRAM;
  LDSTAM_typ           : ade_LDSTAMxLSV4AM;
  LSV4AM_typ           : ade_LDSTAMxLSV4AM;
  LDSTAMxLSV4AM_pos    : ade_pos;
  DAPRAMxLDSTAM_sdir   : ash_sdir;
  LDSTAMxLSV4AM_uacc   : std_logic;
  LDSTAMxLSV4AM_wb     : std_logic;
end record;

Type ade_insn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_insn is record
  pc_8    : std_logic_vector(31 downto 0);
  insn    : std_logic_vector(31 downto 0);
  insntyp : ade_insntyp;
  decinsn : ade_decinsn;
  am      : ade_amode;
  valid   : std_logic;
  id      : std_logic_vector(2 downto 0);
end record;

Type apc_rrstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rrstg is record
  -- operations
  dummy : std_logic;
end record;

Enum apc_rsop_opsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsop_opsrc is (
  apc_opsrc_through,
  apc_opsrc_buf,
  apc_opsrc_alures,
  apc_opsrc_none
);

Enum apc_rsop_bufsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsop_bufsrc is (
  apc_bufsrc_none,
  apc_bufsrc_through,
  apc_bufsrc_alures
);

Enum ash_styp defined in /tmp/build_html/vhdl/arm/libs/armshiefter.vhd

type ash_styp is (
  ash_styp_none,  -- no shieft
  ash_styp_immrot,-- DAPRAM: OP2 immidiate rotated
  ash_styp_simm,  -- DAPRAM: OP2 shieft with imm, LDSTAM: addr v1 reg (adm_LDSTAM_reg) 
  ash_styp_sreg   -- DAPRAM: OP2 shieft with reg  
);

Type apc_rsstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_rsstg is record
  -- operations
  rsop_op1_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_op2_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source
  rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source
  rsop_styp     : ash_styp;        -- RSSTG shieft op
  rsop_sdir     : ash_sdir;        -- RSSTG shieft dir
  -- data
  rs_shieftcarryout : std_logic;   -- RSSTG shiefter carry out
end record;

Enum apc_exop_datasrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exop_datasrc is (
  apc_datasrc_aluout,
  apc_datasrc_buf,
  apc_datasrc_none
);

Enum apc_exop_bufsrc defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exop_bufsrc is (
  apc_exbufsrc_none,
  apc_exbufsrc_aluout,
  apc_exbufsrc_op1
);

Type apc_exstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_exstg is record
  -- operations
  exop_aluop    : std_logic_vector(3 downto 0);  -- EXSTG alu operation
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source
  exop_setcpsr  : std_logic;         -- EXSTG set cpsr
  -- data                                   
  ex_cpsr : apm_cpsr;           -- EXSTG store old cpsr
end record;

Type apc_dmstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_dmstg is record
  dummy : std_logic;
end record;

Type apc_mestg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_mestg is record
  -- operation
  meop_enable : std_logic;
  meop_param  : gdcl_param;
  -- data
  mexc   : std_logic;
end record;

Constant APM_RREAL_U defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

constant APM_RREAL_U : integer := 4;

Constant APM_RREAL_D defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

constant APM_RREAL_D : integer := 0;

Enum slavestate defined in /tmp/build_html/vhdl/sparc/ahbtest.vhd

type slavestate is (idle, error, split, retry, ws1);

Enum dsnoop_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd

type dsnoop_type is (none, slow, fast);

Enum apm_trap defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_trap is (
  apm_trap_reset,   -- reset
  apm_trap_undef,   -- undefined (EXSTG)
  apm_trap_swi,     -- software interrupt (DRSTG)
  apm_trap_prefch,  -- prefetch error (IMSTG)
  apm_trap_dabort,  -- data abort error (MESTG)
  apm_trap_irq,     -- interrupt
  apm_trap_fiq      -- fast interrupt
);

Type apm_trapctrl defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_trapctrl is record
  traptype : apm_trap;
  trap     : std_logic;
end record;

Type apc_wrstg defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_wrstg is record
  -- operation
  wrop_rd      : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  wrop_rdvalid : std_logic;
  wrop_setspsr : std_logic;
  wrop_trap    : apm_trapctrl;
end record;

Type apc_pctrl defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_pctrl is record
  insn : ade_insn;
  valid : std_logic;
  rr : apc_rrstg;
  rs : apc_rsstg;
  ex : apc_exstg;
  dm : apc_dmstg;
  me : apc_mestg;
  wr : apc_wrstg;
  data1 : std_logic_vector(31 downto 0);
  data2 : std_logic_vector(31 downto 0);
end record;

Type apc_pstate defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_pstate is record
  hold_r    : cli_hold;
  nextinsn_v : std_logic;
  dabort_v : std_logic;
  -- active cpsr
  fromEX_cpsr_r : apm_cpsr;
  -- pctrls of all stages from rrstg on 
  fromRR_pctrl_r : apc_pctrl;
  fromRS_pctrl_r : apc_pctrl;
  fromEX_pctrl_r : apc_pctrl;
  fromDM_pctrl_r : apc_pctrl;
  fromME_pctrl_r : apc_pctrl;
  fromWR_pctrl_r : apc_pctrl;
end record;

Type armiu_imstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_imstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   branch_v : std_logic;
   addrvir_v : std_logic_vector(31 downto 0);
end record;

Type armiu_imstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_imstg_typ_out is record
   toFE_addrphy_v   : std_logic_vector(31 downto 0);
   toFE_addrvir_v   : std_logic_vector(31 downto 0);
   toFE_addrvalid_v : std_logic;
   toFE_branch_v    : std_logic;
   toFE_trap_v      : std_logic;
end record;

File /tmp/build_html/vhdl/arm/armiu_imstg.vhd

Type armiu_festg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_festg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   ico   : genic_type_out;
   fromIM_addrphy_v   : std_logic_vector(31 downto 0);
   fromIM_addrvir_v   : std_logic_vector(31 downto 0);
   fromIM_addrvalid_v : std_logic;
   fromIM_branch_v    : std_logic;
   fromIM_trap_v      : std_logic;
end record;

Type ade_feinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_feinsn is record
  insn    : std_logic_vector(31 downto 0);
  pc      : std_logic_vector(31 downto 0);
  pc_vir  : std_logic_vector(31 downto 0);
  valid   : std_logic;
  trap    : std_logic;
end record;

Type armiu_festg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_festg_typ_out is record
   ici   : genic_type_in;
   toDE_insn_r : ade_feinsn;
   toDE_insn_v : ade_feinsn;
end record;

File /tmp/build_html/vhdl/arm/armiu_festg.vhd

Type armiu_destg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_destg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   fromFE_insn_r : ade_feinsn;
   fromFE_insn_v : ade_feinsn;
end record;

Type ade_deinsn defined in /tmp/build_html/vhdl/arm/libs/armdecode.vhd

type ade_deinsn is record
  insn   : ade_insn;
  trap   : std_logic;
end record;

Type armiu_destg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_destg_typ_out is record
   toDR_insn_r : ade_deinsn;
   toDR_insn_v : ade_deinsn;
end record;

File /tmp/build_html/vhdl/arm/armiu_destg.vhd

Enum unit_status_type defined in /tmp/build_html/vhdl/sparc/fp1eu.vhd

type unit_status_type is (free, started, ready);

Type armiu_drstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_drstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromDE_insn_r : ade_deinsn;
   fromDE_insn_v : ade_deinsn;
   fromRR_nextmicro_v : std_logic;
   fromWR_dabort_v : std_logic;

   fromCPDE_accept : std_logic;
   fromCPDE_busy : std_logic;
   fromCPDE_last : std_logic;

end record;

Type apc_micro defined in /tmp/build_html/vhdl/arm/libs/armpctrl.vhd

type apc_micro is record
  pctrl : apc_pctrl;
  valid : std_logic;
  r1, r2 : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  r1_valid, r2_valid : std_logic;
end record;

Type armiu_drstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_drstg_typ_out is record
   nextinsn_v : std_logic;
   toRR_micro_v : apc_micro;
   id : std_logic_vector(2 downto 0);
end record;

File /tmp/build_html/vhdl/arm/armiu_drstg.vhd

Type armiu_rrstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_rrstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromDR_micro_v : apc_micro;                           
   fromEX_alures_v : std_logic_vector(31 downto 0);
   
   fromWR_rd_v : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
   fromWR_rd_valid_v : std_logic;
   fromWR_rd_data_v : std_logic_vector(31 downto 0);
   
   fromCPEX_data : std_logic_vector(31 downto 0);
   fromCPEX_lock : std_logic;
end record;

Type armiu_rrstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_rrstg_typ_out is record
   pctrl_r : apc_pctrl;
   toRS_pctrl_v : apc_pctrl;
   
   toDR_nextmicro_v  : std_logic;
end record;

File /tmp/build_html/vhdl/arm/armiu_rrstg.vhd

Type armiu_rsstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_rsstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromRR_pctrl_v : apc_pctrl;
   fromEX_alures_v : std_logic_vector(31 downto 0);
   fromEX_cpsr_v : apm_cpsr;
end record;

Type armiu_rsstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_rsstg_typ_out is record
   pctrl_r : apc_pctrl;
   toEX_pctrl_v : apc_pctrl;
end record;

File /tmp/build_html/vhdl/arm/armiu_rsstg.vhd

Type apm_spsr defined in /tmp/build_html/vhdl/arm/libs/armpmodel.vhd

type apm_spsr is record
    svc_spsr : apm_cpsr;    
    abt_spsr : apm_cpsr;  
    und_spsr : apm_cpsr;   
    irq_spsr : apm_cpsr;   
    fiq_spsr : apm_cpsr;
end record;

Type armiu_exstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_exstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromRS_pctrl_v : apc_pctrl;

   fromWR_spsr_r  : apm_spsr;
   fromWR_cpsr_v  : apm_cpsr;
   fromWR_cpsrset_v : std_logic;
  
   fromCP_active : std_logic;
end record;

Type armiu_exstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_exstg_typ_out is record
   pctrl_r : apc_pctrl;
   toDM_pctrl_v : apc_pctrl;
   
   cpsr_r : apm_cpsr;
   cpsr_v : apm_cpsr;
   alures_v : std_logic_vector(31 downto 0);
   
   toIM_branch_v : std_logic;
   flush_v : std_logic;
   
end record;

File /tmp/build_html/vhdl/arm/armiu_exstg.vhd

Type armiu_dmstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_dmstg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   fromEX_pctrl_v : apc_pctrl;
end record;

Type armiu_dmstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_dmstg_typ_out is record
   pctrl_r : apc_pctrl;
   toME_pctrl_v : apc_pctrl;
end record;

File /tmp/build_html/vhdl/arm/armiu_dmstg.vhd

Type armiu_mestg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_mestg_typ_in is record
   pstate : apc_pstate;
   flush_v : std_logic;
   
   irqo : irq_iu_out_type;
   fromDM_pctrl_v : apc_pctrl;
end record;

Type armiu_mestg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_mestg_typ_out is record
   pctrl_r : apc_pctrl;
   toWR_pctrl_v : apc_pctrl;
   dci   : gendc_type_in;
end record;

File /tmp/build_html/vhdl/arm/armiu_mestg.vhd

Type armiu_wrstg_typ_in defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_wrstg_typ_in is record
   pstate : apc_pstate;
   fromME_pctrl_v : apc_pctrl;
   dco   : gendc_type_out;
   
   fromCP_data : std_logic_vector(31 downto 0);
end record;

File /tmp/build_html/vhdl/core/ctrl/irqctrl.vhd

Type armiu_wrstg_typ_out defined in /tmp/build_html/vhdl/arm/arm_comp.vhd

type armiu_wrstg_typ_out is record
   pctrl_r : apc_pctrl;

   spsr_r : apm_spsr;

   irqi : irq_iu_in_type;
   
   toIM_branch_v : std_logic;
   toIM_branchaddr_v : std_logic_vector(31 downto 0);
   
   toDR_dabort_v : std_logic;

   toEX_cpsr_v : apm_cpsr;
   toEX_cpsrset_v : std_logic;

   toRR_rd_v : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
   toRR_rd_valid_v : std_logic;
   toRR_rd_data_v : std_logic_vector(31 downto 0);
   
   toCPWR_crd_data_v : std_logic_vector(31 downto 0);
end record;

File /tmp/build_html/vhdl/arm/armiu_wrstg.vhd

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution