Please wait until document has finished loading (reload)

[Donate]

CONFIG_TARGET:cfg_core_arm
CONFIG_IRQ2EN:0
CFG_DCACHE_LSZ:4
CFG_ICACHE_REPL:cfg_repl_rnd
CFG_DCACHE_ALLOCATE:0
CFG_DCACHE_ALGO:rnd
CFG_ICACHE_SZ:1
CFG_ICACHE_LOCK:0
CFG_ICACHE_LSZ:4
CFG_DCACHE_ASSO:1
CFG_DCACHE_TYPE:writethrough
CFG_DCACHE_LOCK:0
CFG_ICACHE_ASSO:1
CFG_DCACHE_REPL:cfg_repl_rnd
CFG_DCACHE_SZ:1
CFG_DCACHE_WB:2
CFG_ICACHE_ALGO:rnd
CONFIG_BOOT_SYSCLK:25000000
CONFIG_IRQ2EN:0
CONFIG_IRQ2CHAN:1
CONFIG_WDOG:0

Enum cfg_core_types defined in /tmp/build_html/vhdl/core/core_config.vhd type cfg_core_types is (cfg_core_arm, cfg_core_sparc, cfg_core_m68k);

Enum cfg_repl_type defined in /tmp/build_html/vhdl/mem/cache/cache_config.vhd type cfg_repl_type is (cfg_repl_rnd, cfg_repl_lrr, cfg_repl_lru );

Enum cache_replace_type defined in /tmp/build_html/vhdl/sparc/leon_target.vhd type cache_replace_type is (lru, lrr, rnd);

If you have question mail to: Konrad Eisele<eiselekd@web.de>, created: Wed Apr 14 13:07:33 WEDT 2004 ;
This is part of the Core distribution